Support RandSoC configurations

bfasst/flows/clock_crank.py

@@ -17,7 +17,7 @@ def __init__(self, design, synth_options=""):
             self,
             design,
             synth_edf=self.vivado_synth_tool.outputs["synth_edf"],
-            constraints_file=self.vivado_synth_tool.outputs["synth_constraints"],
+            constraints_files=self.vivado_synth_tool.outputs["synth_constraints"],
         )
         self.vivado_impl_tool.outputs["clock_crank_tcl"] = (
             self.vivado_impl_tool.build_path / "clock_crank.tcl"

bfasst/flows/opentitan.py

@@ -31,7 +31,7 @@ def __init__(self, design, synth_options=""):
             self,
             design,
             synth_edf=self.vivado_synth_tool.outputs["synth_edf"],
-            constraints_file=self.vivado_synth_tool.outputs["synth_constraints"],
+            constraints_files=self.vivado_synth_tool.outputs["synth_constraints"],
             impl_options={"part": synth_options["part"]},
         )
 

bfasst/flows/rand_soc.py

@@ -6,29 +6,42 @@
 from bfasst.tools.design_create.rand_soc import RandSoC
 from bfasst.tools.impl.vivado_impl import VivadoImpl
 from bfasst.tools.synth.vivado_synth import VivadoSynth
+from bfasst.paths import ROOT_PATH, GMT_TOOLS_PATH
 
 
 class RandSoc(FlowNoDesign):
     """Flow to create random soc block designs in Vivado"""
 
-    def __init__(self, num_designs=1, part=None):
+    def __init__(self, num_designs=1, part=None, randsoc_config_path=None):
         # pylint: disable=duplicate-code
         super().__init__()
 
         # Override default part
         if part is not None:
             self.part = part
 
-        self.rand_soc_tool = RandSoC(self, num_designs=num_designs)
-
-        for design in self.rand_soc_tool.outputs["design_tcl"]:
-            synth_tool = VivadoSynth(self, design.parent)
-            synth_tool.synth_build["tcl_sources"] = [str(design)]
+        # Get configuration of random SoC creator
+        if randsoc_config_path is None:
+            randsoc_config_path = GMT_TOOLS_PATH / "rand_soc" / "default_config.yaml"
+        else:
+            randsoc_config_path = ROOT_PATH / randsoc_config_path
+        assert randsoc_config_path.exists(), f"Config file {randsoc_config_path} does not exist"
+
+        # Create all random designs
+        self.rand_soc_tool = RandSoC(self, num_designs=num_designs, config_path=randsoc_config_path)
+
+        # Build each random design
+        for design_tcl, contraints_tcl in zip(
+            self.rand_soc_tool.outputs["design_tcl"],
+            self.rand_soc_tool.outputs["impl_constraints_tcl"],
+        ):
+            synth_tool = VivadoSynth(self, design_tcl.parent)
+            synth_tool.synth_build["tcl_sources"] = [str(design_tcl)]
             VivadoImpl(
                 self,
-                design.parent,
+                design_tcl.parent,
                 synth_edf=synth_tool.outputs["synth_edf"],
-                constraints_file=synth_tool.outputs["synth_constraints"],
+                constraints_files=(synth_tool.outputs["synth_constraints"], contraints_tcl),
             )
 
     @classmethod

bfasst/flows/rand_soc_dumped.py

@@ -7,29 +7,44 @@
 from bfasst.tools.impl.vivado_impl import VivadoImpl
 from bfasst.tools.synth.vivado_synth import VivadoSynth
 from bfasst.tools.transform.randsoc_dump import RandsocDump
+from bfasst.paths import ROOT_PATH, GMT_TOOLS_PATH
 
 
 class RandSocDumped(FlowNoDesign):
     """Flow to dump bels from random soc block designs with Isoblaze"""
 
-    def __init__(self, num_designs=1, part=None):
+    def __init__(self, num_designs=1, part=None, randsoc_config_path=None):
         # pylint: disable=duplicate-code
         super().__init__()
 
         # Override default part
         if part is not None:
             self.part = part
 
-        self.rand_soc_tool = RandSoC(self, num_designs=num_designs)
-
-        for i, design in enumerate(self.rand_soc_tool.outputs["design_tcl"]):
-            synth_tool = VivadoSynth(self, design.parent)
-            synth_tool.synth_build["tcl_sources"] = [str(design)]
+        # Get configuration of random SoC creator
+        if randsoc_config_path is None:
+            randsoc_config_path = GMT_TOOLS_PATH / "rand_soc" / "default_config.yaml"
+        else:
+            randsoc_config_path = ROOT_PATH / randsoc_config_path
+        assert randsoc_config_path.exists(), f"Config file {randsoc_config_path} does not exist"
+
+        # Create all random designs
+        self.rand_soc_tool = RandSoC(self, num_designs=num_designs, config_path=randsoc_config_path)
+
+        # Build each random design
+        for i, (design_tcl, contraints_tcl) in enumerate(
+            zip(
+                self.rand_soc_tool.outputs["design_tcl"],
+                self.rand_soc_tool.outputs["impl_constraints_tcl"],
+            )
+        ):
+            synth_tool = VivadoSynth(self, design_tcl.parent)
+            synth_tool.synth_build["tcl_sources"] = [str(design_tcl)]
             impl_tool = VivadoImpl(
                 self,
-                design.parent,
+                design_tcl.parent,
                 synth_edf=synth_tool.outputs["synth_edf"],
-                constraints_file=synth_tool.outputs["synth_constraints"],
+                constraints_files=(synth_tool.outputs["synth_constraints"], contraints_tcl),
             )
             RandsocDump(
                 self,

bfasst/flows/vivado.py

@@ -18,7 +18,7 @@ def __init__(self, design, synth_options=None, ooc=False):
             self,
             design,
             synth_edf=self.vivado_synth_tool.outputs["synth_edf"],
-            constraints_file=self.vivado_synth_tool.outputs["synth_constraints"],
+            constraints_files=self.vivado_synth_tool.outputs["synth_constraints"],
             ooc=ooc,
         )
         self.tools = [self.vivado_synth_tool, self.vivado_impl_tool]

bfasst/flows/vivado_bit_analysis.py

@@ -22,7 +22,7 @@ def __init__(self, design, synth_options="", logging_level="INFO"):
             self,
             design,
             synth_edf=self.vivado_synth_tool.outputs["synth_edf"],
-            constraints_file=self.vivado_synth_tool.outputs["synth_constraints"],
+            constraints_files=self.vivado_synth_tool.outputs["synth_constraints"],
         )
         self.xrev_tool = Xray(
             self,

bfasst/flows/vivado_bit_to_netlist.py

@@ -19,7 +19,7 @@ def __init__(self, design, synth_options=""):
             self,
             design,
             synth_edf=self.vivado_synth_tool.outputs["synth_edf"],
-            constraints_file=self.vivado_synth_tool.outputs["synth_constraints"],
+            constraints_files=self.vivado_synth_tool.outputs["synth_constraints"],
         )
         self.xrev_tool = Xray(
             self,

bfasst/flows/vivado_conformal.py

@@ -20,7 +20,7 @@ def __init__(self, design):
             self,
             design,
             synth_edf=self.vivado_synth_tool.outputs["synth_edf"],
-            constraints_file=self.vivado_synth_tool.outputs["synth_constraints"],
+            constraints_files=self.vivado_synth_tool.outputs["synth_constraints"],
         )
         self.xrev_tool = Xray(
             self,

bfasst/flows/vivado_phys_netlist.py

@@ -22,7 +22,7 @@ def __init__(self, design, synth_options="", logging_level="INFO"):
             self,
             design,
             synth_edf=self.vivado_synth_tool.outputs["synth_edf"],
-            constraints_file=self.vivado_synth_tool.outputs["synth_constraints"],
+            constraints_files=self.vivado_synth_tool.outputs["synth_constraints"],
         )
         self.phys_netlist_tool = PhysNetlist(
             self,

bfasst/flows/vivado_phys_netlist_cmp.py

@@ -25,7 +25,7 @@ def __init__(self, design, synth_options="", debug=False, logging_level="INFO"):
             self,
             design,
             synth_edf=self.vivado_synth_tool.outputs["synth_edf"],
-            constraints_file=self.vivado_synth_tool.outputs["synth_constraints"],
+            constraints_files=self.vivado_synth_tool.outputs["synth_constraints"],
         )
         self.phys_netlist_tool = PhysNetlist(
             self,

bfasst/flows/vivado_structural_error_injection.py

@@ -35,7 +35,7 @@ def __init__(self, design, num_runs=100, seed=None, synth_options="", logging_le
             self,
             design,
             synth_edf=self.vivado_synth_tool.outputs["synth_edf"],
-            constraints_file=self.vivado_synth_tool.outputs["synth_constraints"],
+            constraints_files=self.vivado_synth_tool.outputs["synth_constraints"],
         )
         self.phys_netlist_tool = PhysNetlist(
             self,

bfasst/flows/vivado_wafove.py

@@ -20,7 +20,7 @@ def __init__(self, design):
             self,
             design,
             synth_edf=self.vivado_synth_tool.outputs["synth_edf"],
-            constraints_file=self.vivado_synth_tool.outputs["synth_constraints"],
+            constraints_files=self.vivado_synth_tool.outputs["synth_constraints"],
         )
         self.xrev_tool = Xray(
             self,

bfasst/flows/vivado_yosys_cmp.py

@@ -20,7 +20,7 @@ def __init__(self, design):
             self,
             design,
             synth_edf=self.vivado_synth_tool.outputs["synth_edf"],
-            constraints_file=self.vivado_synth_tool.outputs["synth_constraints"],
+            constraints_files=self.vivado_synth_tool.outputs["synth_constraints"],
         )
         self.xrev_tool = Xray(
             self,

bfasst/tools/design_create/rand_soc.py

@@ -10,11 +10,12 @@
 class RandSoC(ToolBase):
     """Tool to create a random SoC"""
 
-    def __init__(self, flow, num_designs):
+    def __init__(self, flow, num_designs, config_path):
         super().__init__(flow)
         self.build_path = BUILD_PATH / "rand_soc"
         self._my_dir_path = pathlib.Path(__file__).parent.resolve()
         self.num_designs = num_designs
+        self.config_path = config_path
         self._init_outputs()
         self.rule_snippet_path = TOOLS_PATH / "design_create" / "rand_soc_rules.ninja"
 
@@ -29,6 +30,7 @@ def create_build_snippets(self):
                     f,
                     {
                         "design_dir_path": design_dir_path,
+                        "config_path": self.config_path,
                         "seed": i,
                         "rand_soc_source_files": " ".join((str(s) for s in rand_soc_pkg_files)),
                         "part": self.flow.part,
@@ -40,9 +42,11 @@ def create_build_snippets(self):
 
     def _init_outputs(self):
         self.outputs["design_tcl"] = []
+        self.outputs["impl_constraints_tcl"] = []
         for i in range(self.num_designs):
             design_dir_path = self.build_path / f"design_{i}"
             self.outputs["design_tcl"].append(design_dir_path / "design.tcl")
+            self.outputs["impl_constraints_tcl"].append(design_dir_path / "impl_constraints.tcl")
 
     def add_ninja_deps(self, deps):
         self._add_ninja_deps_default(deps, __file__)

bfasst/tools/design_create/rand_soc_build.ninja.mustache

@@ -1,5 +1,6 @@
-build {{ design_dir_path }}/design.tcl: rand_soc | {{ rand_soc_source_files }}
+build {{ design_dir_path }}/design.tcl {{ design_dir_path }}/impl_constraints.tcl: rand_soc | {{ rand_soc_source_files }}
     design_dir_path = {{ design_dir_path }}
+    config_path = {{ config_path }}
     seed = {{ seed }}
     part = {{ part }}
 

bfasst/tools/design_create/rand_soc_rules.ninja

@@ -1,4 +1,4 @@
 rule rand_soc
-    command = python third_party/gmt_tools/rand_soc/main.py $design_dir_path --seed $seed --part $part
+    command = python third_party/gmt_tools/rand_soc/main.py $design_dir_path $config_path --seed $seed --part $part
     description = generate a random SoC in $design_dir_path
 

bfasst/tools/impl/vivado_impl.py

@@ -5,17 +5,19 @@
 from bfasst import config
 from bfasst.tools.impl.impl_tool import ImplTool
 from bfasst.paths import COMMON_TOOLS_PATH, BFASST_UTILS_PATH
-from bfasst.utils.general import json_write_if_changed
+from bfasst.utils.general import ensure_tuple, json_write_if_changed
 
 
 class VivadoImpl(ImplTool):
     """Tool to create Vivado implementation ninja snippets."""
 
-    def __init__(self, flow, design, synth_edf, constraints_file="", ooc=False, impl_options=""):
+    def __init__(self, flow, design, synth_edf, constraints_files="", ooc=False, impl_options=""):
         super().__init__(flow, design)
         self.ooc = ooc
 
-        self.constraints_file = constraints_file if not self.ooc else ""
+        self.constraints_file = [
+            str(f) for f in ensure_tuple(constraints_files if not self.ooc else "")
+        ]
         self.synth_edf = synth_edf
 
         self.build_path = (
@@ -26,7 +28,7 @@ def __init__(self, flow, design, synth_edf, constraints_file="", ooc=False, impl
         self._my_dir_path = pathlib.Path(__file__).parent
 
         self._init_outputs()
-        self.inputs_str = {"xdc": str(self.constraints_file), "synth_edf": str(self.synth_edf)}
+        self.inputs_str = {"xdc": self.constraints_file, "synth_edf": str(self.synth_edf)}
         self.outputs_str = {k: str(v) for k, v in self.outputs.items()}
         self.impl_build = {
             "part": self.flow.part,
@@ -63,7 +65,6 @@ def create_build_snippets(self):
             {
                 "in_context": not self.ooc,
                 "impl_output": str(self.build_path),
-                "synth_constraints": str(self.constraints_file),
                 "synth_edf": str(self.synth_edf),
                 "impl_library": self._my_dir_path,
                 "cwd": self.build_path,

bfasst/tools/impl/vivado_impl_build.ninja.mustache

@@ -4,7 +4,7 @@ build {{outputs.impl_tcl}}: template {{outputs.impl_json}} {{impl_library}}/viva
 build {{outputs.reports_tcl}}: template {{outputs.impl_json}} {{impl_library}}/vivado_impl_reports.tcl.mustache
 build {{outputs.run_tcl}}: template {{outputs.impl_json}} {{common_tools_path }}/vivado_top_tcl.mustache | {{#tcl_sources}} {{.}} {{/tcl_sources}}
 
-build {{outputs.impl_verilog }} {{outputs.impl_edf}} {{outputs.impl_dcp}} {{outputs.bitstream }} {{outputs.utilization}}: vivado {{outputs.run_tcl}} | {{inputs.synth_edf}} {{inputs.xdc}} {{#outputs.clock_crank_tcl}} {{.}} {{/outputs.clock_crank_tcl}} {{outputs.setup_tcl}} {{outputs.impl_tcl}} {{outputs.reports_tcl}}
+build {{outputs.impl_verilog }} {{outputs.impl_edf}} {{outputs.impl_dcp}} {{outputs.bitstream }} {{outputs.utilization}}: vivado {{outputs.run_tcl}} | {{inputs.synth_edf}} {{#inputs.xdc}} {{ . }} {{/inputs.xdc}} {{#outputs.clock_crank_tcl}} {{.}} {{/outputs.clock_crank_tcl}} {{outputs.setup_tcl}} {{outputs.impl_tcl}} {{outputs.reports_tcl}}
     journal = {{outputs.journal}}
     log = {{outputs.log}}
 

bfasst/tools/impl/vivado_impl_setup.tcl.mustache

@@ -3,7 +3,6 @@ set_property top_file {{ inputs.synth_edf }} [current_fileset]
 link_design -part {{ part }}
 {{#inputs.xdc}}
 read_xdc {{ . }}
-
 {{/inputs.xdc}}
 {{#clocks}}
 create_clock -period {{period}} -name {{ name }}_gen {{#waveform}} -waveform { {{.}} } {{/waveform}} [get_ports {{ name }}]

resources/randsoc/dataset5.yaml

@@ -0,0 +1,7 @@
+flow: RandSocDumped
+
+num_designs: 6000
+
+part: xc7a200tlffv1156-2L
+
+randsoc_config_path: resources/randsoc/randsoc_configs/dataset5.yaml

resources/randsoc/randsoc_configs/dataset5.yaml

@@ -0,0 +1,20 @@
+available_ip:
+  - class: Accumulator
+  - class: AxiCdma
+  - class: AxiHwicap
+    max: 1
+  - class: AxiTimer
+  - class: Dft
+  - class: Emc
+  - class: Gpio
+  - class: Microblaze
+  - class: Uartlite
+  - class: XadcWiz
+    max: 1
+  - class: AxiEthernetLite
+  - class: AxiIic
+  - class: AxiQuadSpi
+
+
+min_ip: 3
+max_ip: 18