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Attribute to retain cells during optimization (#2303)
I added a new boolean attribute that indicates which cells (and uses of cells) should be preserved during optimizations. I check for the attribute in the `dead-cell-removal` pass, so the pass doesn't optimize those cells when it would otherwise do so. (@ekiwi and I got to the bottom of the errors I was experiencing yesterday) The attribute is currently called `@protected`, but if anyone has suggestions about what the attribute should be named that would be helpful! ## Example The test file `tests/passes/dead-cell-removal-protected.futil` differs from `tests/passes/dead-cell-removal.futil` by a single line, where we add `@protected` to unused register `unused_reg`: ``` $ diff tests/passes/dead-cell-removal.futil tests/passes/dead-cell-removal-protected.futil 30c30 < unused_reg = std_reg(32); --- > @Protected unused_reg = std_reg(32); ``` The expect files showing the result of running `dead-cell-removal` indicate that the pass retained `unused_reg` because of the `@protected` attribute: ``` $ diff tests/passes/dead-cell-removal.expect tests/passes/dead-cell-removal-protected.expect 26a27 > @Protected unused_reg = std_reg(32); ```
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import "primitives/core.futil"; | ||
import "primitives/memories/comb.futil"; | ||
component main(@go go: 1, @clk clk: 1, @reset reset: 1) -> (@done done: 1) { | ||
cells { | ||
@protected add0 = std_add(32); | ||
add1 = std_add(32); | ||
x_0 = std_reg(32); | ||
} | ||
wires { | ||
group upd0 { | ||
add0.left = x_0.out; | ||
add0.right = 32'd1; | ||
x_0.in = add0.out; | ||
x_0.write_en = 1'd1; | ||
upd0[done] = x_0.done ? 1'd1; | ||
} | ||
group upd1 { | ||
add1.left = x_0.out; | ||
add1.right = 32'd1; | ||
x_0.in = add1.out; | ||
x_0.write_en = 1'd1; | ||
upd1[done] = x_0.done ? 1'd1; | ||
} | ||
} | ||
control { | ||
seq { | ||
upd0; | ||
upd1; | ||
} | ||
} | ||
} |
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Original file line number | Diff line number | Diff line change |
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//-p cell-share -p remove-ids | ||
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||
import "primitives/core.futil"; | ||
import "primitives/memories/comb.futil"; | ||
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// testing that @protected overrides @share | ||
component main() -> () { | ||
cells { | ||
@protected add0 = std_add(32); | ||
add1 = std_add(32); | ||
x_0 = std_reg(32); | ||
} | ||
wires { | ||
group upd0 { | ||
add0.left = x_0.out; | ||
add0.right = 32'd1; | ||
x_0.in = add0.out; | ||
x_0.write_en = 1'd1; | ||
upd0[done] = x_0.done ? 1'd1; | ||
} | ||
group upd1 { | ||
add1.left = x_0.out; | ||
add1.right = 32'd1; | ||
x_0.in = add1.out; | ||
x_0.write_en = 1'd1; | ||
upd1[done] = x_0.done ? 1'd1; | ||
} | ||
} | ||
control { | ||
seq { | ||
upd0; | ||
upd1; | ||
} | ||
} | ||
} |
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,41 @@ | ||
import "primitives/core.futil"; | ||
import "primitives/memories/comb.futil"; | ||
component add(left: 32, right: 32, @go go: 1, @clk clk: 1, @reset reset: 1) -> (out: 32, @done done: 1) { | ||
cells { | ||
adder = std_add(32); | ||
outpt = std_reg(32); | ||
} | ||
wires { | ||
group do_add { | ||
adder.left = left; | ||
adder.right = right; | ||
outpt.in = adder.out; | ||
outpt.write_en = 1'd1; | ||
do_add[done] = outpt.done; | ||
} | ||
} | ||
control { | ||
seq { | ||
do_add; | ||
} | ||
} | ||
} | ||
component main(@go go: 1, @clk clk: 1, @reset reset: 1) -> (out: 32, @done done: 1) { | ||
cells { | ||
used_reg = std_reg(32); | ||
used_le = std_le(1); | ||
@protected unused_reg = std_reg(32); | ||
my_add = add(); | ||
add_input = std_reg(32); | ||
} | ||
wires { | ||
used_reg.in = used_le.out ? 32'd10; | ||
out = used_reg.out; | ||
} | ||
control { | ||
invoke my_add( | ||
left = add_input.out, | ||
right = add_input.out | ||
)(); | ||
} | ||
} |
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,41 @@ | ||
// -p dead-cell-removal | ||
import "primitives/core.futil"; | ||
import "primitives/memories/comb.futil"; | ||
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component add(left: 32, right: 32) -> (out: 32) { | ||
cells { | ||
adder = std_add(32); | ||
outpt = std_reg(32); | ||
} | ||
wires { | ||
group do_add { | ||
adder.left = left; | ||
adder.right = right; | ||
outpt.in = adder.out; | ||
outpt.write_en = 1'd1; | ||
do_add[done] = outpt.done; | ||
} | ||
} | ||
control { | ||
seq { | ||
do_add; | ||
} | ||
} | ||
} | ||
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component main() -> (out: 32) { | ||
cells { | ||
used_reg = std_reg(32); | ||
used_le = std_le(1); | ||
@protected unused_reg = std_reg(32); | ||
my_add = add(); | ||
add_input = std_reg(32); | ||
} | ||
wires { | ||
used_reg.in = used_le.out ? 32'd10; | ||
out = used_reg.out; | ||
} | ||
control { | ||
invoke my_add(left = add_input.out, right = add_input.out)(); | ||
} | ||
} |