fixed bug where compiler generates OR guards instead of AND

calyxir · Dec 17, 2024 · 470506d · 470506d
1 parent 1f00f4b
commit 470506d
Showing 1 changed file with 8 additions and 1 deletion.
diff --git a/calyx-backend/src/verilog.rs b/calyx-backend/src/verilog.rs
@@ -880,13 +880,20 @@ impl<'a> std::fmt::Display for VerilogPortRef<'a> {
 
 fn unflattened_guard(guard: &ir::Guard<Nothing>) -> String {
     match guard {
-        Guard::Or(left, right) | Guard::And(left, right) => {
+        Guard::Or(left, right) => {
             format!(
                 "({}) | ({})",
                 unflattened_guard(left),
                 unflattened_guard(right)
             )
         }
+        Guard::And(left, right) => {
+            format!(
+                "({}) & ({})",
+                unflattened_guard(left),
+                unflattened_guard(right)
+            )
+        }
         Guard::CompOp(comp, left, right) => {
             let op = match comp {
                 ir::PortComp::Eq => "==",