[fud2] First pass for custom testbench support (#2063)

* committing old version of testbench generator

* [WIP] reading json

* remove extraneous files

* Parse json from YXI file

* small fixes

* Fix for comb_mem being interpreted as Sequential

* Fixed YXI test using combinational memory

* [WIP] Midway incorporating custom testbench generator to fud2

* inputs to FIRRTL should contain ref, not @external

* [WIP] First pass at very convoluted way to get FIRRTL and testbench generated.

* Fix pipeline through firrtl-noverify. Need to make path through firrtl (for verilator)

* Add refmem build for verilator

* Supporting FIRRTL w FIRRTL primitives

* Fix small bugs

* Remove testbench rsrcing

* Some script documentation

* Remove duplicate comb_mem_d1

* Fixed MissingConfig issue. Now need to double check and update snaps

* Change test snapshots and rename setups

* Fix tests according to current fud2 behavior

* Update documentation comment

* Replace dummy script with dummy command

* Fix tests according to previous change

* Added memories.sv hack to Icarus as well

* Change test snapshots for Icarus (produce and use memories.sv)

* Create new rules that either do or don't involve memories.sv instead of creating a blank file

* Fix documentation comment

calyx-backend/src/firrtl.rs

@@ -109,7 +109,15 @@ fn emit_component<F: io::Write>(
     // Cells
     for cell in comp.cells.iter() {
         let cell_borrowed = cell.as_ref().borrow();
-        if cell_borrowed.type_name().is_some() {
+        let is_external = cell
+            .borrow()
+            .get_attribute(ir::BoolAttr::External)
+            .is_some();
+        if is_external {
+            // The FIRRTL compiler cannot read/write memories, so we must use ref.
+            panic!("FIRRTL backend only works on ref, not @external!");
+        }
+        if cell_borrowed.type_name().is_some() && !is_external {
             let module_name = match &cell_borrowed.prototype {
                 ir::CellType::Primitive {
                     name,

calyx-ir/src/utils.rs

@@ -57,14 +57,14 @@ impl GetMemInfo for Vec<RRC<Cell>> {
                   let mut dimension_sizes: Vec<u64> = Vec::new();
                   let mut idx_sizes: Vec<u64> = Vec::new();
                   let dimensions: u64;
-                  //let mem_cell_type = mem.prototype.get_name().unwrap(); //i.e. "comb_mem_d1"
-                  let mem_type : MemoryType = if mem.is_comb_cell() {
+                  let mem_cell_type = mem.prototype.get_name().unwrap(); //i.e. "comb_mem_d1"
+                  let mem_type : MemoryType = if mem_cell_type.to_string().contains("comb") {
                     MemoryType::Combinational
                   } else {
                     MemoryType::Sequential
                   };
 
-                  match mem.prototype.get_name().unwrap().as_ref() {
+                  match mem_cell_type.as_ref() {
                       "comb_mem_d1" | "seq_mem_d1" => {
                         dimension_sizes.push(mem.get_parameter("SIZE").unwrap());
                         dimensions = 1;