@data carried over to external memories (#2019)

* make changes * tests * small patch * tests * docs: * solved it * rewrite tests
calyxir · Apr 24, 2024 · 56b99c5 · 56b99c5
1 parent 619fbcc
commit 56b99c5
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Showing 9 changed files with 31 additions and 9 deletions.
diff --git a/calyx-backend/src/verilog.rs b/calyx-backend/src/verilog.rs
@@ -499,7 +499,12 @@ fn is_data_port(pr: &RRC<ir::Port>) -> bool {
     if let ir::PortParent::Cell(cwr) = &port.parent {
         let cr = cwr.upgrade();
         let cell = cr.borrow();
-        if cell.attributes.has(ir::BoolAttr::Data) {
+        // For cell.is_this() ports that were externalized, we already checked
+        // that the parent cell had the `@data` attribute.
+        if cell.attributes.has(ir::BoolAttr::Data)
+            || (cell.is_this()
+                & port.attributes.has(ir::BoolAttr::Externalized))
+        {
             return true;
         }
     }

diff --git a/calyx-frontend/src/attribute.rs b/calyx-frontend/src/attribute.rs
@@ -64,6 +64,9 @@ pub enum BoolAttr {
     #[strum(serialize = "promoted")]
     /// denotes a static component or control promoted from dynamic
     Promoted,
+    #[strum(serialize = "externalized")]
+    /// Denotes a port that has been externalized (i.e., dumped into signature)
+    Externalized,
 }
 impl From<BoolAttr> for Attribute {
     fn from(attr: BoolAttr) -> Self {

diff --git a/calyx-opt/src/passes/dump_ports.rs b/calyx-opt/src/passes/dump_ports.rs
@@ -40,6 +40,9 @@ where
     for cell_ref in &ext_cells {
         let cell = cell_ref.borrow();
         log::debug!("cell `{}' removed", cell.name());
+        // We need this information because we might want to attach the `@data`
+        // attribute to some of the ports.
+        let is_data_cell = cell.attributes.has(ir::BoolAttr::Data);
 
         // If we do not eliminate the @clk and @reset ports, we may
         // get signals conflicting the original @clk and @reset signals of
@@ -62,12 +65,23 @@ where
         for port_ref in ports_inline {
             let canon = port_ref.borrow().canonical();
             let port = port_ref.borrow();
+            // We might want to insert
+            let mut new_port_attrs =
+                if is_data_cell & port.attributes.has(ir::BoolAttr::Data) {
+                    let mut attrs = ir::Attributes::default();
+                    attrs.insert(ir::BoolAttr::Data, 1);
+                    attrs
+                } else {
+                    ir::Attributes::default()
+                };
+            new_port_attrs.insert(ir::BoolAttr::Externalized, 1);
+
             let new_port = ir::rrc(ir::Port {
                 name: component.generate_name(format_port_name(&canon)),
                 width: port.width,
                 direction: port.direction.clone(),
                 parent: ir::PortParent::Cell(WRC::from(&component.signature)),
-                attributes: ir::Attributes::default(),
+                attributes: new_port_attrs,
             });
             component
                 .signature

diff --git a/tests/passes/compile-invoke/invoke-ref.expect b/tests/passes/compile-invoke/invoke-ref.expect
@@ -1,5 +1,5 @@
 import "primitives/compile.futil";
-component foo(@go go: 1, @clk clk: 1, @reset reset: 1, r_out: 32, r_done: 1) -> (@done done: 1, r_in: 32, r_write_en: 1) {
+component foo(@go go: 1, @clk clk: 1, @reset reset: 1, @externalized r_out: 32, @externalized r_done: 1) -> (@done done: 1, @externalized r_in: 32, @externalized r_write_en: 1) {
   cells {
   }
   wires {

diff --git a/tests/passes/compile-invoke/ref-chain.expect b/tests/passes/compile-invoke/ref-chain.expect
@@ -20,7 +20,7 @@ component main(@go go: 1, @clk clk: 1, @reset reset: 1) -> (@done done: 1) {
     }
   }
 }
-component incr(@go go: 1, @clk clk: 1, @reset reset: 1, value_out: 32, value_done: 1) -> (@done done: 1, value_in: 32, value_write_en: 1) {
+component incr(@go go: 1, @clk clk: 1, @reset reset: 1, @externalized value_out: 32, @externalized value_done: 1) -> (@done done: 1, @externalized value_in: 32, @externalized value_write_en: 1) {
   cells {
     ih = incr_helper();
   }
@@ -40,7 +40,7 @@ component incr(@go go: 1, @clk clk: 1, @reset reset: 1, value_out: 32, value_don
     }
   }
 }
-component incr_helper(@go go: 1, @clk clk: 1, @reset reset: 1, value_out: 32, value_done: 1) -> (@done done: 1, value_in: 32, value_write_en: 1) {
+component incr_helper(@go go: 1, @clk clk: 1, @reset reset: 1, @externalized value_out: 32, @externalized value_done: 1) -> (@done done: 1, @externalized value_in: 32, @externalized value_write_en: 1) {
   cells {
     incr_value = std_add(32);
   }

diff --git a/tests/passes/compile-invoke/ref-invoke.expect b/tests/passes/compile-invoke/ref-invoke.expect
@@ -1,5 +1,5 @@
 import "primitives/compile.futil";
-component foo(@go go: 1, @clk clk: 1, @reset reset: 1, m_out: 32, m_done: 1) -> (@done done: 1, m_in: 32, m_write_en: 1) {
+component foo(@go go: 1, @clk clk: 1, @reset reset: 1, @externalized m_out: 32, @externalized m_done: 1) -> (@done done: 1, @externalized m_in: 32, @externalized m_write_en: 1) {
   cells {
     r = std_reg(32);
   }

diff --git a/tests/passes/compile-invoke/ref.expect b/tests/passes/compile-invoke/ref.expect
@@ -1,5 +1,5 @@
 import "primitives/compile.futil";
-component foo(@go go: 1, @clk clk: 1, @reset reset: 1, r_out: 32, r_done: 1) -> (@done done: 1, r_in: 32, r_write_en: 1) {
+component foo(@go go: 1, @clk clk: 1, @reset reset: 1, @externalized r_out: 32, @externalized r_done: 1) -> (@done done: 1, @externalized r_in: 32, @externalized r_write_en: 1) {
   cells {
   }
   wires {

diff --git a/tests/passes/compile-invoke/static-ref.expect b/tests/passes/compile-invoke/static-ref.expect
@@ -1,6 +1,6 @@
 import "primitives/core.futil";
 import "primitives/memories/comb.futil";
-static<2> component add_one(@go go: 1, @clk clk: 1, @reset reset: 1, out_read_data: 32, out_done: 1) -> (@done done: 1, out_addr0: 1, out_write_data: 32, out_write_en: 1) {
+static<2> component add_one(@go go: 1, @clk clk: 1, @reset reset: 1, @externalized out_read_data: 32, @externalized out_done: 1) -> (@done done: 1, @externalized out_addr0: 1, @externalized out_write_data: 32, @externalized out_write_en: 1) {
   cells {
     add = std_add(32);
     r = std_reg(32);

diff --git a/tests/passes/externalize.expect b/tests/passes/externalize.expect
@@ -1,6 +1,6 @@
 import "primitives/core.futil";
 import "primitives/memories/comb.futil";
-component main(@go go: 1, @clk clk: 1, @reset reset: 1, A_read_data: 32, A_done: 1) -> (@done done: 1, A_addr0: 4, A_write_data: 32, A_write_en: 1, A_clk: 1, A_reset: 1) {
+component main(@go go: 1, @clk clk: 1, @reset reset: 1, @externalized A_read_data: 32, @externalized A_done: 1) -> (@done done: 1, @externalized A_addr0: 4, @externalized A_write_data: 32, @externalized A_write_en: 1, @externalized A_clk: 1, @externalized A_reset: 1) {
   cells {
     B = comb_mem_d1(32, 16, 4);
     state = std_reg(32);