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change while line to for line due to format checking
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jiahanxie353 committed Dec 17, 2024
1 parent eda6ead commit 5c6d93e
Showing 1 changed file with 2 additions and 2 deletions.
4 changes: 2 additions & 2 deletions calyx-backend/src/verilog.rs
Original file line number Diff line number Diff line change
Expand Up @@ -235,10 +235,10 @@ impl Backend for VerilogBackend {
if cmd.status.success() {
// Post-process morty output
let stdout = String::from_utf8_lossy(&cmd.stdout);
let mut lines = stdout.lines();
let lines = stdout.lines();
let mut skip_next_line = false;

while let Some(line) = lines.next() {
for line in lines {
if skip_next_line {
skip_next_line = false;
continue;
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