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[Cider] rename interp to cider (#2376)
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Finally, rename the cider library to be `cider` instead of `interp`.
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EclecticGriffin authored Dec 13, 2024
1 parent 426e107 commit 727912a
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Showing 237 changed files with 81 additions and 75 deletions.
8 changes: 4 additions & 4 deletions .github/workflows/rust.yml
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Expand Up @@ -111,14 +111,14 @@ jobs:
uses: actions-rs/cargo@v1
with:
command: build
args: --all --all-features --manifest-path /home/calyx/interp/Cargo.toml
args: --all --all-features --manifest-path /home/calyx/cider/Cargo.toml

- name: Set location of cider binary
run: |
fud c stages.interpreter.exec /home/calyx/target/debug/cider
- name: Runt tests
working-directory: /home/calyx/interp/tests
working-directory: /home/calyx/cider/tests
run: |
# Run the remaining tests
runt -x '(numeric types correctness and parsing)' -d -o fail
Expand All @@ -127,13 +127,13 @@ jobs:
uses: actions-rs/cargo@v1
with:
command: test
args: --manifest-path /home/calyx/interp/Cargo.toml
args: --manifest-path /home/calyx/cider/Cargo.toml

- name: Source code doc tests
uses: actions-rs/cargo@v1
with:
command: test
args: --manifest-path /home/calyx/interp/Cargo.toml --doc
args: --manifest-path /home/calyx/cider/Cargo.toml --doc

compiler:
name: Test Compiler
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78 changes: 39 additions & 39 deletions Cargo.lock

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2 changes: 1 addition & 1 deletion Cargo.toml
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Expand Up @@ -8,7 +8,7 @@ members = [
"calyx-stdlib",
"calyx-backend",
"calyx-lsp",
"interp",
"cider",
"web/rust",
"tools/data_gen",
"cider-dap",
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4 changes: 2 additions & 2 deletions cider-dap/Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -9,15 +9,15 @@ edition = "2021"
dap = { git = "https://github.com/sztomi/dap-rs", tag = "v0.4.1-alpha1" }
thiserror = "1.*"
serde_json = "1.0"
serde.workspace= true
serde.workspace = true
owo-colors = "^3.5"
argh = "0.1"
slog = "2.7.0"
slog-term = "2.8.0"
slog-async = "2.7.0"
baa = "0.14"

interp = { path = "../interp" }
cider = { path = "../cider" }

[[bin]]
name = "cider-dap"
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8 changes: 4 additions & 4 deletions cider-dap/src/adapter.rs
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@@ -1,14 +1,14 @@
use crate::error::AdapterResult;
use baa::BitVecOps;
use cider::debugger::commands::ParsedGroupName;
use cider::debugger::source::structures::NewSourceMap;
use cider::debugger::{OwnedDebugger, StoppedReason};
use cider::flatten::flat_ir::base::{GlobalCellIdx, PortValue};
use dap::events::{Event, OutputEventBody, StoppedEventBody};
use dap::types::{
self, Breakpoint, Scope, Source, SourceBreakpoint, StackFrame, Thread,
Variable,
};
use interp::debugger::commands::ParsedGroupName;
use interp::debugger::source::structures::NewSourceMap;
use interp::debugger::{OwnedDebugger, StoppedReason};
use interp::flatten::flat_ir::base::{GlobalCellIdx, PortValue};
use std::collections::{HashMap, HashSet};
use std::path::PathBuf;

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2 changes: 1 addition & 1 deletion interp/Cargo.toml → cider/Cargo.toml
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
[package]
name = "interp"
name = "cider"
version = "0.1.1"
authors = ["The Calyx authors"]
edition = "2021"
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6 changes: 3 additions & 3 deletions interp/src/macros.rs → cider/src/macros.rs
Original file line number Diff line number Diff line change
Expand Up @@ -29,7 +29,7 @@ macro_rules! lit_or_id {
#[macro_export]
/// Helper macro to generate port bindings.
/// ```
/// # use interp::port_bindings;
/// # use cider::port_bindings;
/// port_bindings![ binds;
/// r#in -> (16, 32),
/// write_en -> (1, 1)
Expand All @@ -46,7 +46,7 @@ macro_rules! port_bindings {

/// Helper macro to generate validation checks for the input passed to primitives
/// ```
/// # use interp::validate;
/// # use cider::validate;
/// # use baa::BitVecValue;
/// # let input = [("left", [4,4,4,4])];
/// # let inputs = &input;
Expand All @@ -72,7 +72,7 @@ macro_rules! validate {
/// Helper macro to generate validation checks for the input passed to
/// primitives, does not error on unknown ports
/// ```
/// # use interp::validate_friendly;
/// # use cider::validate_friendly;
/// # use baa::BitVecValue;
/// # let input = [("left", [4,4,4,4])];
/// # let inputs = &input;
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4 changes: 2 additions & 2 deletions interp/src/main.rs → cider/src/main.rs
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@
use argh::FromArgs;

use calyx_utils::OutputFile;
use interp::{
use cider::{
configuration,
debugger::{Debugger, DebuggerInfo, DebuggerReturnStatus},
errors::CiderResult,
Expand Down Expand Up @@ -120,7 +120,7 @@ fn main() -> CiderResult<()> {
.build();

let command = opts.mode.unwrap_or(Command::Interpret(CommandInterpret {}));
let i_ctx = interp::flatten::setup_simulation(
let i_ctx = cider::flatten::setup_simulation(
&opts.file,
&opts.lib_path,
opts.skip_verification,
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14 changes: 10 additions & 4 deletions interp/tests/runt.toml → cider/tests/runt.toml
Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,7 @@ paths = ["multi-comp/*.futil"]
cmd = """
fud2 --from calyx --to dat \
--through cider \
-s cider.flags="--dump-registers" \
-s cider.flags="--dump-registers --check-data-race" \
{}
"""
timeout = 10
Expand All @@ -39,7 +39,7 @@ paths = ["complex/*.futil"]
cmd = """
fud2 --from calyx --to dat \
--through cider \
-s cider.flags="--dump-registers" \
-s cider.flags="--dump-registers --check-data-race" \
{}
"""
timeout = 10
Expand Down Expand Up @@ -83,7 +83,7 @@ expect_dir = "control"
name = "invoke"
paths = ["control/invoke/*.futil"]
cmd = """
fud2 {} --from calyx --to dat --through cider -s sim.data={}.data -s calyx.args="--log off"
fud2 {} --from calyx --to dat --through cider -s sim.data={}.data -s calyx.args="--log off" -s cider.flags="--check-data-race"
"""
timeout = 10

Expand All @@ -93,7 +93,8 @@ paths = ["control/invoke/*.futil"]
cmd = """
fud2 {} --from calyx --to dat --through cider \
-s cider.calyx-passes=" -p compile-invoke" \
-s sim.data={}.data -s calyx.args="--log off"
-s sim.data={}.data -s calyx.args="--log off" \
-s cider.flags="--check-data-race"
"""

[[tests]]
Expand Down Expand Up @@ -165,6 +166,7 @@ fud2 --from calyx --to dat \
--through cider \
-s sim.data={}.data \
-s calyx.args="--log off" \
-s cider.flags="--check-data-race" \
{}
"""

Expand All @@ -177,6 +179,7 @@ fud2 --from calyx --to dat \
-s sim.data={}.data \
-s calyx.args="--log off" \
-s cider.calyx-passes=" -p compile-invoke" \
-s cider.flags="--check-data-race" \
{}
"""

Expand Down Expand Up @@ -204,6 +207,7 @@ fud2 --from calyx --to dat \
--through cider \
-s calyx.args="--log off" \
-s sim.data={}.data \
-s cider.flags="--check-data-race" \
{}
"""

Expand All @@ -215,6 +219,7 @@ fud2 --from calyx --to dat \
--through cider \
-s sim.data={}.data \
-s calyx.args="--log off" \
-s cider.flags="--check-data-race" \
{}
"""

Expand All @@ -226,6 +231,7 @@ fud2 --from dahlia --to dat \
--through cider \
-s sim.data={}.data \
-s calyx.args="--log off" \
-s cider.flags="--check-data-race" \
{}
"""
timeout = 180
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2 changes: 1 addition & 1 deletion tools/cider-data-converter/Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@ version = "0.1.0"
# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html

[dependencies]
interp = { path = "../../interp" }
cider = { path = "../../cider" }
serde = { workspace = true }
serde_json = { workspace = true, features = ["arbitrary_precision"] }
itertools = { workspace = true }
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16 changes: 8 additions & 8 deletions tools/cider-data-converter/src/converter.rs
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
use super::json_data::*;
use interp::serialization::*;
use cider::serialization::*;
use itertools::Itertools;
use num_bigint::{BigInt, BigUint, ToBigInt};
use num_rational::BigRational;
Expand Down Expand Up @@ -162,11 +162,11 @@ fn float_to_rational(float: f64) -> BigRational {

fn unroll_float(
val: f64,
format: &interp::serialization::FormatInfo,
format: &cider::serialization::FormatInfo,
round_float: bool,
) -> Vec<u8> {
match *format {
interp::serialization::FormatInfo::Fixed {
cider::serialization::FormatInfo::Fixed {
signed,
int_width,
frac_width,
Expand Down Expand Up @@ -225,7 +225,7 @@ fn unroll_float(
.take((frac_width + int_width).div_ceil(8) as usize)
.collect::<Vec<_>>()
}
interp::serialization::FormatInfo::IEEFloat { width, .. } => {
cider::serialization::FormatInfo::IEEFloat { width, .. } => {
match width {
32 => Vec::from((val as f32).to_le_bytes().as_slice()),
64 => Vec::from(val.to_le_bytes().as_slice()),
Expand Down Expand Up @@ -272,13 +272,13 @@ fn format_data(declaration: &MemoryDeclaration, data: &[u8]) -> ParseVec {
let chunk_stream =
data.chunks_exact(width.div_ceil(8) as usize).map(|chunk| {
match declaration.format {
interp::serialization::FormatInfo::Bitnum {
cider::serialization::FormatInfo::Bitnum {
signed, ..
} => {
let int = parse_bytes(chunk, width, signed);
Number::from_str(&int.to_str_radix(10)).unwrap()
}
interp::serialization::FormatInfo::Fixed {
cider::serialization::FormatInfo::Fixed {
signed,
int_width,
frac_width,
Expand All @@ -289,7 +289,7 @@ fn format_data(declaration: &MemoryDeclaration, data: &[u8]) -> ParseVec {

Number::from_f64(float).unwrap()
}
interp::serialization::FormatInfo::IEEFloat {
cider::serialization::FormatInfo::IEEFloat {
width,
..
} => {
Expand Down Expand Up @@ -411,7 +411,7 @@ mod tests {
let int_width = 16;
let frac_width = 16;

let format = interp::serialization::FormatInfo::Fixed {
let format = cider::serialization::FormatInfo::Fixed {
signed,
int_width,
frac_width,
Expand Down
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