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fix dot output
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ayakayorihiro committed Nov 17, 2024
1 parent 3621af0 commit 7c118ea
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Showing 2 changed files with 12 additions and 13 deletions.
13 changes: 6 additions & 7 deletions tools/profiler/new-parse-vcd.py
Original file line number Diff line number Diff line change
Expand Up @@ -328,8 +328,7 @@ def create_traces(active_element_probes_info, call_stack_probes_info, cell_calle
while len(cell_worklist) > 0:
current_cell = cell_worklist.pop()
current_component = cells_to_components[current_cell]
print(f"current component: {current_component}")
covered_units_in_component = {"main"} # collect all of the units we've covered.
covered_units_in_component = set() # collect all of the units we've covered.
# this is so silly... but catch all active units that are groups in this component.
units_to_cover = set(filter(lambda unit: not unit.is_cell and unit.component == current_component, timeline_map[i]))
# find all enables from control. these are all units that either (1) don't have any maps in call_stack_probes_info, or (2) have no active parent calls in call_stack_probes_info
Expand Down Expand Up @@ -374,10 +373,10 @@ def create_traces(active_element_probes_info, call_stack_probes_info, cell_calle
if cell_calling_probe.is_active_at_cycle(i) and cell_active_probe.is_active_at_cycle(i):
cell_worklist.append(cell_active_probe.name)
# invoker group is the parent of the cell.
i_mapping[cell_active_probe.name] = i_mapping[f"{current_cell}.{cell_invoker}"] + [cell_active_probe.shortname]
cell_component = cells_to_components[cell_active_probe.name]
i_mapping[cell_active_probe.name] = i_mapping[f"{current_cell}.{cell_invoker}"] + [f"{cell_active_probe.shortname} [{cell_component}]"]
parents.add(f"{current_cell}.{cell_invoker}")


for elem in i_mapping:
if elem not in parents:
new_timeline_map[i].append(i_mapping[elem])
Expand All @@ -400,8 +399,8 @@ def create_output(timeline_map, out_dir):
for stack in timeline_map[i]:
acc = "\t"
for stack_elem in stack[0:-1]:
acc += stack_elem + " -> "
acc += stack[-1] + ";\n"
acc += f'"{stack_elem}" -> '
acc += f'"{stack[-1]}" ;\n'
# for stack_elem in stack[0:-1]:
# acc += stack_elem.shortname + " -> "
# acc += stack[-1].shortname + ";\n"
Expand Down Expand Up @@ -443,7 +442,7 @@ def main(vcd_filename, cells_json_file, out_dir):
# cycles per group.
new_timeline_map = create_traces(converter.active_elements_info, converter.call_stack_probe_info, converter.cell_invoke_caller_probe_info, converter.clock_cycles, cells_to_components, main_component)

# create_output(new_timeline_map, out_dir)
create_output(new_timeline_map, out_dir)


if __name__ == "__main__":
Expand Down
12 changes: 6 additions & 6 deletions tools/profiler/new-profiler-approach.sh
Original file line number Diff line number Diff line change
Expand Up @@ -84,10 +84,10 @@ echo "[${SCRIPT_NAME}] Using FSM info and VCD file to obtain cycle level counts"
) &> ${LOGS_DIR}/gol-process

# Convert all dot files to pdf
# TREES_PDF_DIR=${OUT_DIR}-pdf
# mkdir -p ${TREES_PDF_DIR}
# for f in $( ls ${OUT_DIR} | grep dot$ ); do
# dot -Tpng ${OUT_DIR}/${f} > ${TREES_PDF_DIR}/${f}.png
# done
TREES_PDF_DIR=${OUT_DIR}-pdf
mkdir -p ${TREES_PDF_DIR}
for f in $( ls ${OUT_DIR} | grep dot$ ); do
dot -Tpng ${OUT_DIR}/${f} > ${TREES_PDF_DIR}/${f}.png
done

# ${FLAMEGRAPH_DIR}/flamegraph.pl --countname="cycles" ${OUT_DIR}/flame.folded > ${OUT_DIR}/flame.svg
${FLAMEGRAPH_DIR}/flamegraph.pl --countname="cycles" ${OUT_DIR}/flame.folded > ${OUT_DIR}/flame.svg

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