Skip to content

Commit

Permalink
Merge branch 'main' into tidy-queue-teststing
Browse files Browse the repository at this point in the history
  • Loading branch information
anshumanmohan authored Jun 18, 2024
2 parents fff1e7e + 04add67 commit 844f542
Show file tree
Hide file tree
Showing 14 changed files with 519 additions and 247 deletions.
4 changes: 2 additions & 2 deletions calyx-py/calyx/builder.py
Original file line number Diff line number Diff line change
Expand Up @@ -734,7 +734,7 @@ def bitwise_flip_reg(self, reg, cellname=None):

def incr(self, reg, val=1, signed=False, cellname=None, static=False):
"""Inserts wiring into `self` to perform `reg := reg + val`."""
cellname = cellname or f"{reg.name}_incr"
cellname = cellname or self.generate_name(f"{reg.name}_incr_{val}")
width = reg.infer_width_reg()
add_cell = self.add(width, cellname, signed)
group = (
Expand All @@ -753,7 +753,7 @@ def incr(self, reg, val=1, signed=False, cellname=None, static=False):

def decr(self, reg, val=1, signed=False, cellname=None):
"""Inserts wiring into `self` to perform `reg := reg - val`."""
cellname = cellname or f"{reg.name}_decr"
cellname = cellname or self.generate_name(f"{reg.name}_decr_{val}")
width = reg.infer_width_reg()
sub_cell = self.sub(width, cellname, signed)
with self.group(f"{cellname}_group") as decr_group:
Expand Down
File renamed without changes.
6 changes: 3 additions & 3 deletions calyx-py/test/correctness/queues/binheap.data
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
{
"mem": {
"out": {
"data": [
0,
0,
Expand All @@ -20,7 +20,7 @@
"format": {
"is_signed": false,
"numeric_type": "bitnum",
"width": 64
"width": 32
}
}
}
}
12 changes: 6 additions & 6 deletions calyx-py/test/correctness/queues/binheap.expect
Original file line number Diff line number Diff line change
@@ -1,14 +1,14 @@
{
"mem": [
"out": [
3,
6,
6,
8,
9,
9,
10,
12,
0,
0,
0,
0,
0,
3,
0,
0,
0,
Expand Down
Loading

0 comments on commit 844f542

Please sign in to comment.