Xsim working with ip

fud2/rsrc/xsim.tcl

@@ -0,0 +1,87 @@
+proc lshift listVar {
+  upvar 1 $listVar L
+  set r [lindex $L 0]
+  set L [lreplace $L [set L 0] 0]
+  return $r
+}
+
+#-------------------------------------------------------
+# Process command line arguments
+#-------------------------------------------------------
+set error 0
+set help 0
+set cycle_limit 50000
+set data ""
+set verilog {}
+set args $argv
+# if {[llength $args] == 0} { incr help }; # Uncomment if necessary
+while {[llength $args]} {
+  set flag [lshift args]
+  switch -exact -- $flag {
+    -i -
+    -ip-tcl {
+      set ip_script [lshift args]
+    }
+    -d -
+    -data {
+      set data [lshift args]
+    }
+    -c -
+    -cycle-limit {
+      set cycle_limit [lshift args]
+    }
+    -h -
+    -help {
+      incr help
+    }
+    default {
+      if {[string match "-*" $flag]} {
+       puts " ERROR - option '$flag' is not a valid option."
+       incr error
+      } else {
+        lappend verilog $flag
+      }
+    }
+  }
+}
+
+if {$help} {
+  set callerflag [lindex [info level [expr [info level] -1]] 0]
+  # <-- HELP
+  puts [format {
+ Usage: %s
+       [-ports|-p <listOfPorts>]
+       [-verbose|-v]
+       [-help|-h]
+
+ Description: xxxxxxxxxxxxxxxxxxx.
+        xxxxxxxxxxxxxxxxxxx.
+
+ Example:
+   %s -port xxxxxxxxxxxxxxx
+
+  } $callerflag $callerflag ]
+  # HELP -->
+  return -code ok {}
+}
+
+# Check validity of arguments. Increment $error to generate an error
+
+if {$error} {
+  return -code error {Oops, something is not correct}
+}
+
+set dir [pwd]
+
+create_project -force prj1
+add_files $verilog
+if {[info exists ip_script]} {
+  source $ip_script
+}
+set_property top toplevel [get_fileset sim_1]
+set_property -name {xsim.simulate.runtime} -value {all} -objects [get_filesets sim_1]
+puts $cycle_limit
+set_property verilog_define [subst {CYCLE_LIMIT=$cycle_limit DATA=$dir/$data}] [get_filesets sim_1]
+launch_simulation
+close_project
+return -code ok {}

fud2/scripts/verilator.rhai

@@ -8,7 +8,7 @@ fn verilator_setup(e) {
    e.config_var_or("cycle-limit", "sim.cycle_limit", "500000000");
    e.rule(
         "verilator-compile-standalone-tb",
-        "$verilator $in tb.sv -DCYCLE_LIMIT=$cycle-limit -DDATA=\"$datadir\" --trace --binary --top-module toplevel -fno-inline -Mdir $out-dir",
+        "$verilator $in tb.sv -DCYCLE_LIMIT=$cycle-limit -DDATA=$datadir --trace --binary --top-module toplevel -fno-inline -Mdir $out-dir",
    );
    e.rule(
         "verilator-compile-custom-tb",

fud2/scripts/xilinx.rhai

@@ -20,7 +20,7 @@ fn xilinx_setup(e) {
     );
     e.arg("pool", "console");  // Lets Ninja stream the tool output "live."
 
-    // Compile an `.xo` file to an `.xclbin` file, which is where the actual EDA work occurs.
+    // Compile an `.xo` ile to an `.xclbin` file, which is where the actual EDA work occurs.
     e.config_var_or("xilinx-mode", "xilinx.mode", "hw_emu");
     e.config_var_or("platform", "xilinx.device", "xilinx_u50_gen3x16_xdma_201920_3");
     e.rule(

fud2/scripts/xsim.rhai

@@ -0,0 +1,85 @@
+import "rtl_sim" as sim;
+import "testbench" as tb;
+import "calyx" as c;
+
+export const xsim_setup = xsim_setup;
+fn xsim_setup(e) {
+    e.config_var("vivado-dir", "xilinx.vivado");
+    e.config_var_or("cycle-limit", "sim.cycle_limit", "500000000");
+    e.rsrc("xsim.tcl");
+    let has_tcl = !e.config_or("xsim.ip_tcl", "").is_empty();
+    if has_tcl {
+        let tcl_name = e.config_val("xsim.ip_tcl");
+        let tcl_path = e.external_path(tcl_name);
+        e.var_("ip_tcl", tcl_path);
+        print(tcl_path);
+        e.rule(
+           "xsim-standalone-tb",
+           "$vivado-dir/bin/vivado -mode batch -source xsim.tcl -tclargs -c $cycle-limit -d $datadir -i $ip_tcl tb.sv verilog.sv > $out",
+        );
+        e.rule(
+           "xsim-custom-tb",
+           "$vivado-dir/bin/vivado -mode batch -source xsim.tcl -tclargs -c $cycle-limit -d $datadir -i $ip_tcl tb.sv verilog.sv memories.sv > $out",
+        );
+    } else {
+        e.rule(
+           "xsim-standalone-tb",
+           "$vivado-dir/bin/vivado -mode batch -source xsim.tcl -tclargs -c $cycle-limit -d $datadir tb.sv verilog.sv > $out",
+        );
+        e.rule(
+           "xsim-custom-tb",
+           "$vivado-dir/bin/vivado -mode batch -source xsim.tcl -tclargs -c $cycle-limit -d $datadir tb.sv verilog.sv memories.sv > $out",
+        );
+    }
+}
+
+export const xsim_build = xsim_build;
+fn xsim_build(e, input, output, datadir, standalone_tb) {
+   if standalone_tb {
+      e.build_cmd(
+        [output],
+        "xsim-standalone-tb",
+        [input],
+        ["tb.sv", "xsim.tcl", datadir],
+      );
+   } else {
+      e.build_cmd(
+         [output],
+         "xsim-custom-tb",
+         [input],
+         ["tb.sv", "memories.sv", "xsim.tcl", datadir],
+      );
+   }
+}
+
+op(
+   "xsim",
+   [sim::sim_setup, tb::standalone_setup, xsim_setup],
+   c::verilog_state,
+   sim::dat,
+   |e, input, output| { 
+      xsim_build(e, input, "sim.log", "$datadir", true);
+      e.build_cmd(
+         [output],
+         "json-data",
+         ["$datadir", "sim.log"],
+         ["json-dat.py"],
+      );
+   },
+);
+
+op(
+   "xsim-refmem",
+   [sim::sim_setup, tb::custom_setup, xsim_setup],
+   tb::verilog_refmem,
+   sim::dat,
+   |e, input, output| {
+      xsim_build(e, input, "sim.log", "$datadir", false);
+      e.build_cmd(
+         [output],
+         "json-data",
+         ["$datadir", "sim.log"],
+         ["json-dat.py"],
+      );
+   }
+);