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Remove use of always_comb
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rachitnigam committed Nov 3, 2024
1 parent 8294be8 commit a753450
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Showing 3 changed files with 4 additions and 55 deletions.
2 changes: 1 addition & 1 deletion primitives/binary_operators.sv
Original file line number Diff line number Diff line change
Expand Up @@ -146,7 +146,7 @@ module std_fp_div_pipe #(
running <= running;
end

always_comb begin
always @* begin
if (acc >= {1'b0, right}) begin
acc_next = acc - right;
{acc_next, quotient_next} = {acc_next[WIDTH-1:0], quotient, 1'b1};
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Original file line number Diff line number Diff line change
Expand Up @@ -327,7 +327,7 @@ module std_fp_div_pipe #(
running <= running;
end

always_comb begin
always @* begin
if (acc >= {1'b0, right}) begin
acc_next = acc - right;
{acc_next, quotient_next} = {acc_next[WIDTH-1:0], quotient, 1'b1};
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55 changes: 2 additions & 53 deletions yxi/tests/axi/read-compute-write/seq-mem-vec-add-verilog.expect
Original file line number Diff line number Diff line change
@@ -1,53 +1,2 @@
{
"A0": {
"data": [
1,
3,
7,
15,
31,
63,
127,
255
],
"format": {
"numeric_type": "bitnum",
"is_signed": false,
"width": 32
}
},
"B0": {
"data": [
1,
1,
1,
1,
1,
1,
1,
1
],
"format": {
"numeric_type": "bitnum",
"is_signed": false,
"width": 32
}
},
"Sum0": {
"data": [
2,
4,
8,
16,
32,
64,
128,
256
],
"format": {
"numeric_type": "bitnum",
"is_signed": false,
"width": 32
}
}
}
---CODE---
1

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