Add width parameter to pipelined_mult primitive (#1748)

* add newest iteration of mul primitives

* revert old primitive changes

* remove std_mult_pipe in favor of std_mult_seq

* Revert mult_pipe name change for now

* Update binary_operators.sv

* add pipelined_mult parameter to regression tests

---------

Co-authored-by: Andrew Butt <[email protected]>

primitives/binary_operators.futil

@@ -86,7 +86,6 @@ extern "binary_operators.sv" {
   /// =================== Unsigned, Bitnum =========================
   /// Other unsigned bitnum primitives are found in the core library,
   /// since they're required for FSM encoding.
-
   primitive std_mult_pipe<"state_share"=1>[WIDTH](
     @clk clk: 1,
     @reset reset: 1,

primitives/binary_operators.sv

@@ -762,4 +762,4 @@ module std_signext #(
         );
     end
   `endif
-endmodule
+endmodule

primitives/pipelined.futil

@@ -1,12 +1,12 @@
 extern "pipelined.sv" {
     // A latency-sensitive multiplier that takes 4 cycles to compute its result.
-    static<4> primitive pipelined_mult (
+    static<4> primitive pipelined_mult[WIDTH] (
         @clk clk: 1,
         @reset reset: 1,
-        left: 32,
-        right: 32
+        left: WIDTH,
+        right: WIDTH
     ) -> (
-        out: 32
+        out: WIDTH
     );
 
     // A latency-sensitive multiplier that takes 4 cycles to compute its result.
@@ -20,4 +20,5 @@ extern "pipelined.sv" {
     ) -> (
         out: WIDTH
     );
-}
+
+}

primitives/pipelined.sv

@@ -1,34 +1,34 @@
 
 /// This is mostly used for testing the static guarantees currently.
 /// A realistic implementation would probably take four cycles.
-module pipelined_mult (
+module pipelined_mult #(
+    parameter WIDTH = 32
+) (
     input wire clk,
     input wire reset,
     // inputs
-    input wire [31:0] left,
-    input wire [31:0] right,
+    input wire [WIDTH-1:0] left,
+    input wire [WIDTH-1:0] right,
     // The input has been committed
-    output wire [31:0] out
+    output wire [WIDTH-1:0] out
 );
 
-logic [31:0] lt, rt, buff0, buff1, buff2, tmp_prod;
+logic [WIDTH-1:0] buff0, buff1, buff2, buff3, tmp_prod;
 
-assign out = buff2;
-assign tmp_prod = lt * rt;
+assign out = buff3;
+assign tmp_prod = left * right;
 
 always_ff @(posedge clk) begin
     if (reset) begin
-        lt <= 0;
-        rt <= 0;
         buff0 <= 0;
         buff1 <= 0;
         buff2 <= 0;
+        buff3 <= 0;
     end else begin
-        lt <= left;
-        rt <= right;
         buff0 <= tmp_prod;
         buff1 <= buff0;
         buff2 <= buff1;
+        buff3 <= buff2;
     end
 end
 

tests/correctness/static-control/static-mult-dot-product.futil

@@ -3,7 +3,7 @@ import "primitives/pipelined.futil";
 
 component main() -> () {
     cells {
-        mul = pipelined_mult();
+        mul = pipelined_mult(32);
         @external left = std_mem_d1(32, 10, 4);
         @external right = std_mem_d1(32, 10, 4);
         @external out = std_mem_d1(32, 10, 4);