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finally done with clippy i hope
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EclecticGriffin committed Dec 10, 2024
1 parent 9c184f9 commit bc49bfb
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion calyx-backend/src/verilog.rs
Original file line number Diff line number Diff line change
Expand Up @@ -419,7 +419,7 @@ fn cell_instance(cell: &ir::Cell) -> Option<v::Instance> {
);
} else {
param_binding.iter().for_each(|(name, value)| {
if *value > (std::i32::MAX as u64) {
if *value > (i32::MAX as u64) {
panic!(
"Parameter value {} for `{}` cannot be represented using 32 bits",
value,
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