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Fixes verilog generation and scripts to support xsim
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@andrewb1999
andrewb1999 committed Nov 16, 2024
1 parent fa298e9 commit bd9763b
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Showing 4 changed files with 47 additions and 33 deletions.
57 changes: 37 additions & 20 deletions calyx-backend/src/verilog.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -329,7 +329,7 @@ fn emit_component<F: io::Write>(
if let Some(check) =
emit_guard_disjoint_check(dst, asgns, &pool, true)
{
writeln!(f, "always_comb begin")?;
writeln!(f, "always_ff @(posedge clk) begin")?;
writeln!(f, " {check}")?;
writeln!(f, "end")?;
}
Expand Down Expand Up @@ -763,16 +763,17 @@ fn emit_guard<F: std::io::Write>(
//==========================================
/// Generates code of the form:
/// ```
/// string DATA;
/// `define STRINGIFY(x) `"x`"
/// string data = `STRINGIFY(`DATA);
/// int CODE;
/// initial begin
/// CODE = $value$plusargs("DATA=%s", DATA);
/// $display("DATA: %s", DATA);
/// $readmemh({DATA, "/<mem_name>.dat"}, <mem_name>.mem);
/// CODE = $value$plusargs("data=%s", data);
/// $display("data: %s", data);
/// $readmemh($sformatf("%s/<mem_name>.dat", data), <mem_name>.mem);
/// ...
/// end
/// final begin
/// $writememh({DATA, "/<mem_name>.out"}, <mem_name>.mem);
/// $writememh($sformatf("%s/<mem_name>.out", data), <mem_name>.mem);
/// end
/// ```
fn memory_read_write(comp: &ir::Component) -> Vec<v::Stmt> {
Expand Down Expand Up @@ -805,14 +806,15 @@ fn memory_read_write(comp: &ir::Component) -> Vec<v::Stmt> {
}

// Import futil helper library.
let data_decl = v::Stmt::new_rawstr("string DATA;".to_string());
let stringify_decl = v::Stmt::new_rawstr("`define STRINGIFY(x) `\"x`\"".to_string());
let data_decl = v::Stmt::new_rawstr("string data = `STRINGIFY(`DATA);".to_string());
let code_decl = v::Stmt::new_rawstr("int CODE;".to_string());

let plus_args = v::Sequential::new_blk_assign(
v::Expr::Ref("CODE".to_string()),
v::Expr::new_call(
"$value$plusargs",
vec![v::Expr::new_str("DATA=%s"), v::Expr::new_ref("DATA")],
vec![v::Expr::new_str("data=%s"), v::Expr::new_ref("data")],
),
);

Expand All @@ -824,8 +826,8 @@ fn memory_read_write(comp: &ir::Component) -> Vec<v::Stmt> {
.add_seq(v::Sequential::new_seqexpr(v::Expr::new_call(
"$display",
vec![
v::Expr::new_str("DATA (path to meminit files): %s"),
v::Expr::new_ref("DATA"),
v::Expr::new_str("data (path to meminit files): %s"),
v::Expr::new_ref("data"),
],
)));

Expand All @@ -834,12 +836,19 @@ fn memory_read_write(comp: &ir::Component) -> Vec<v::Stmt> {
initial_block.add_seq(v::Sequential::new_seqexpr(v::Expr::new_call(
"$readmemh",
vec![
v::Expr::Concat(v::ExprConcat {
exprs: vec![
v::Expr::new_str(&format!("/{}.dat", name)),
v::Expr::new_ref("DATA"),
// v::Expr::Concat(v::ExprConcat {
// exprs: vec![
// v::Expr::new_str(&format!("/{}.dat", name)),
// v::Expr::new_ref("data"),
// ],
// })
v::Expr::new_call(
"$sformatf",
vec![
v::Expr::new_str(&format!("%s/{}.dat", name)),
v::Expr::new_ref("data"),
],
}),
),
v::Expr::new_ipath(&format!("{}.{}", name, mem_access_str)),
],
)));
Expand All @@ -852,18 +861,26 @@ fn memory_read_write(comp: &ir::Component) -> Vec<v::Stmt> {
final_block.add_seq(v::Sequential::new_seqexpr(v::Expr::new_call(
"$writememh",
vec![
v::Expr::Concat(v::ExprConcat {
exprs: vec![
v::Expr::new_str(&format!("/{}.out", name)),
v::Expr::new_ref("DATA"),
// v::Expr::Concat(v::ExprConcat {
// exprs: vec![
// v::Expr::new_str(&format!("/{}.out", name)),
// v::Expr::new_ref("data"),
// ],
// }),
v::Expr::new_call(
"$sformatf",
vec![
v::Expr::new_str(&format!("%s/{}.out", name)),
v::Expr::new_ref("data"),
],
}),
),
v::Expr::new_ipath(&format!("{}.{}", name, mem_access_str)),
],
)));
});

vec![
stringify_decl,
data_decl,
code_decl,
v::Stmt::new_parallel(v::Parallel::new_process(initial_block)),
Expand Down
17 changes: 7 additions & 10 deletions fud2/rsrc/tb.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@ localparam RESET_CYCLES = 3;

// Cycle counter. Make this signed to catch errors with cycle simulation
// counts.
logic signed [63:0] cycle_count;
logic signed [63:0] cycle_count = 64'd0;

always_ff @(posedge clk) begin
cycle_count <= cycle_count + 1;
Expand All @@ -35,15 +35,15 @@ string OUT;
// Disable VCD tracing
int NOTRACE;
// Maximum number of cycles to simulate
longint CYCLE_LIMIT;
longint cycle_limit = `CYCLE_LIMIT;
// Dummy variable to track value returned by $value$plusargs
int CODE;

initial begin
CODE = $value$plusargs("OUT=%s", OUT);
CODE = $value$plusargs("CYCLE_LIMIT=%d", CYCLE_LIMIT);
if (CYCLE_LIMIT != 0) begin
$display("cycle limit set to %d", CYCLE_LIMIT);
CODE = $value$plusargs("cycle_limit=%d", cycle_limit);
if (cycle_limit != 0) begin
$display("cycle limit set to %d", cycle_limit);
end
CODE = $value$plusargs("NOTRACE=%d", NOTRACE);
if (NOTRACE == 0) begin
Expand All @@ -55,10 +55,7 @@ initial begin
end

// Initial values
go = 0;
clk = 0;
reset = 1;
cycle_count = 0;

forever begin
#10 clk = ~clk;
Expand All @@ -67,8 +64,8 @@ initial begin
// cycle.
$display("Simulated %d cycles", cycle_count - RESET_CYCLES - 1);
$finish;
end else if (cycle_count != 0 && cycle_count == CYCLE_LIMIT + RESET_CYCLES) begin
$display("reached limit of %d cycles", CYCLE_LIMIT);
end else if (cycle_count != 0 && cycle_count == cycle_limit + RESET_CYCLES) begin
$display("reached limit of %d cycles", cycle_limit);
$finish;
end
end
Expand Down
2 changes: 1 addition & 1 deletion fud2/scripts/rtl_sim.rhai
View file
Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@ fn sim_setup(e) {
// Rule for simulation execution.
e.rule(
"sim-run",
"./$bin +DATA=$datadir +CYCLE_LIMIT=$cycle-limit $args > $out",
"./$bin $args > $out",
);

// More shared configuration.
Expand Down
4 changes: 2 additions & 2 deletions fud2/scripts/verilator.rhai
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,11 +8,11 @@ fn verilator_setup(e) {
e.config_var_or("cycle-limit", "sim.cycle_limit", "500000000");
e.rule(
"verilator-compile-standalone-tb",
"$verilator $in tb.sv --trace --binary --top-module toplevel -fno-inline -Mdir $out-dir",
"$verilator $in tb.sv -DCYCLE_LIMIT=$cycle-limit -DDATA=\"$datadir\" --trace --binary --top-module toplevel -fno-inline -Mdir $out-dir",
);
e.rule(
"verilator-compile-custom-tb",
"$verilator $in tb.sv memories.sv --trace --binary --top-module toplevel -fno-inline -Mdir $out-dir",
"$verilator $in tb.sv memories.sv -DCYCLE_LIMIT=$cycle-limit -DDATA=$datadir --trace --binary --top-module toplevel -fno-inline -Mdir $out-dir",
);
e.rule("cp", "cp $in $out");
}
Expand Down

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