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* Test simulation targets * Slight cleanup * A bunch more tests
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--- | ||
source: fud2/tests/tests.rs | ||
description: emit calyx -> debug | ||
--- | ||
build-tool = fud2 | ||
rule get-rsrc | ||
command = $build-tool get-rsrc $out | ||
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# RTL simulation | ||
python = python3 | ||
build json-dat.py: get-rsrc | ||
rule hex-data | ||
command = $python json-dat.py --from-json $in $out | ||
rule json-data | ||
command = $python json-dat.py --to-json $out $in | ||
build tb.sv: get-rsrc | ||
sim_data = /test/data.json | ||
datadir = sim_data | ||
build $datadir: hex-data $sim_data | json-dat.py | ||
rule sim-run | ||
command = ./$bin +DATA=$datadir +CYCLE_LIMIT=$cycle-limit $args > $out | ||
cycle-limit = 500000000 | ||
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# Calyx compiler | ||
calyx-base = /test/calyx | ||
calyx-exe = $calyx-base/target/debug/calyx | ||
rule calyx | ||
command = $calyx-exe -l $calyx-base -b $backend $args $in > $out | ||
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# Cider interpreter | ||
cider-exe = $calyx-base/target/debug/cider | ||
rule cider | ||
command = $cider-exe -l $calyx-base --raw --data data.json $in > $out | ||
rule cider-debug | ||
command = $cider-exe -l $calyx-base --data data.json $in debug || true | ||
pool = console | ||
build interp-dat.py: get-rsrc | ||
python = python3 | ||
rule dat-to-interp | ||
command = $python interp-dat.py --to-interp $in | ||
rule interp-to-dat | ||
command = $python interp-dat.py --from-interp $in $sim_data > $out | ||
build data.json: dat-to-interp $sim_data | interp-dat.py | ||
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# build targets | ||
build _pseudo_debug: cider-debug stdin | data.json | ||
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default _pseudo_debug |
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--- | ||
source: fud2/tests/tests.rs | ||
description: emit calyx -> dat through icarus | ||
--- | ||
build-tool = fud2 | ||
rule get-rsrc | ||
command = $build-tool get-rsrc $out | ||
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# Calyx compiler | ||
calyx-base = /test/calyx | ||
calyx-exe = $calyx-base/target/debug/calyx | ||
rule calyx | ||
command = $calyx-exe -l $calyx-base -b $backend $args $in > $out | ||
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# RTL simulation | ||
python = python3 | ||
build json-dat.py: get-rsrc | ||
rule hex-data | ||
command = $python json-dat.py --from-json $in $out | ||
rule json-data | ||
command = $python json-dat.py --to-json $out $in | ||
build tb.sv: get-rsrc | ||
sim_data = /test/data.json | ||
datadir = sim_data | ||
build $datadir: hex-data $sim_data | json-dat.py | ||
rule sim-run | ||
command = ./$bin +DATA=$datadir +CYCLE_LIMIT=$cycle-limit $args > $out | ||
cycle-limit = 500000000 | ||
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# Icarus Verilog | ||
iverilog = iverilog | ||
rule icarus-compile | ||
command = $iverilog -g2012 -o $out tb.sv $in | ||
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# build targets | ||
build stdin.sv: calyx stdin | ||
backend = verilog | ||
args = --disable-verify | ||
build stdin.exe: icarus-compile stdin.sv | tb.sv | ||
build sim.log: sim-run stdin.exe $datadir | ||
bin = stdin.exe | ||
args = +NOTRACE=1 | ||
build stdin.json: json-data $datadir sim.log | json-dat.py | ||
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default stdin.json |
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--- | ||
source: fud2/tests/tests.rs | ||
description: emit calyx -> vcd through icarus | ||
--- | ||
build-tool = fud2 | ||
rule get-rsrc | ||
command = $build-tool get-rsrc $out | ||
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# Calyx compiler | ||
calyx-base = /test/calyx | ||
calyx-exe = $calyx-base/target/debug/calyx | ||
rule calyx | ||
command = $calyx-exe -l $calyx-base -b $backend $args $in > $out | ||
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# RTL simulation | ||
python = python3 | ||
build json-dat.py: get-rsrc | ||
rule hex-data | ||
command = $python json-dat.py --from-json $in $out | ||
rule json-data | ||
command = $python json-dat.py --to-json $out $in | ||
build tb.sv: get-rsrc | ||
sim_data = /test/data.json | ||
datadir = sim_data | ||
build $datadir: hex-data $sim_data | json-dat.py | ||
rule sim-run | ||
command = ./$bin +DATA=$datadir +CYCLE_LIMIT=$cycle-limit $args > $out | ||
cycle-limit = 500000000 | ||
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# Icarus Verilog | ||
iverilog = iverilog | ||
rule icarus-compile | ||
command = $iverilog -g2012 -o $out tb.sv $in | ||
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# build targets | ||
build stdin.sv: calyx stdin | ||
backend = verilog | ||
args = --disable-verify | ||
build stdin.exe: icarus-compile stdin.sv | tb.sv | ||
build sim.log stdin.vcd: sim-run stdin.exe $datadir | ||
bin = stdin.exe | ||
args = +NOTRACE=0 +OUT=stdin.vcd | ||
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default stdin.vcd |
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--- | ||
source: fud2/tests/tests.rs | ||
description: emit calyx -> dat through interp | ||
--- | ||
build-tool = fud2 | ||
rule get-rsrc | ||
command = $build-tool get-rsrc $out | ||
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# RTL simulation | ||
python = python3 | ||
build json-dat.py: get-rsrc | ||
rule hex-data | ||
command = $python json-dat.py --from-json $in $out | ||
rule json-data | ||
command = $python json-dat.py --to-json $out $in | ||
build tb.sv: get-rsrc | ||
sim_data = /test/data.json | ||
datadir = sim_data | ||
build $datadir: hex-data $sim_data | json-dat.py | ||
rule sim-run | ||
command = ./$bin +DATA=$datadir +CYCLE_LIMIT=$cycle-limit $args > $out | ||
cycle-limit = 500000000 | ||
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# Calyx compiler | ||
calyx-base = /test/calyx | ||
calyx-exe = $calyx-base/target/debug/calyx | ||
rule calyx | ||
command = $calyx-exe -l $calyx-base -b $backend $args $in > $out | ||
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# Cider interpreter | ||
cider-exe = $calyx-base/target/debug/cider | ||
rule cider | ||
command = $cider-exe -l $calyx-base --raw --data data.json $in > $out | ||
rule cider-debug | ||
command = $cider-exe -l $calyx-base --data data.json $in debug || true | ||
pool = console | ||
build interp-dat.py: get-rsrc | ||
python = python3 | ||
rule dat-to-interp | ||
command = $python interp-dat.py --to-interp $in | ||
rule interp-to-dat | ||
command = $python interp-dat.py --from-interp $in $sim_data > $out | ||
build data.json: dat-to-interp $sim_data | interp-dat.py | ||
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# build targets | ||
build interp_out.json: cider stdin | data.json | ||
build stdin.json: interp-to-dat interp_out.json | $sim_data interp-dat.py | ||
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default stdin.json |
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@@ -0,0 +1,49 @@ | ||
--- | ||
source: fud2/tests/tests.rs | ||
description: emit calyx -> dat through verilator | ||
--- | ||
build-tool = fud2 | ||
rule get-rsrc | ||
command = $build-tool get-rsrc $out | ||
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||
# Calyx compiler | ||
calyx-base = /test/calyx | ||
calyx-exe = $calyx-base/target/debug/calyx | ||
rule calyx | ||
command = $calyx-exe -l $calyx-base -b $backend $args $in > $out | ||
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||
# RTL simulation | ||
python = python3 | ||
build json-dat.py: get-rsrc | ||
rule hex-data | ||
command = $python json-dat.py --from-json $in $out | ||
rule json-data | ||
command = $python json-dat.py --to-json $out $in | ||
build tb.sv: get-rsrc | ||
sim_data = /test/data.json | ||
datadir = sim_data | ||
build $datadir: hex-data $sim_data | json-dat.py | ||
rule sim-run | ||
command = ./$bin +DATA=$datadir +CYCLE_LIMIT=$cycle-limit $args > $out | ||
cycle-limit = 500000000 | ||
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# Verilator | ||
verilator = verilator | ||
cycle-limit = 500000000 | ||
rule verilator-compile | ||
command = $verilator $in tb.sv --trace --binary --top-module TOP -fno-inline -Mdir $out-dir | ||
rule cp | ||
command = cp $in $out | ||
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# build targets | ||
build stdin.sv: calyx stdin | ||
backend = verilog | ||
build verilator-out/VTOP: verilator-compile stdin.sv | tb.sv | ||
out-dir = verilator-out | ||
build stdin.exe: cp verilator-out/VTOP | ||
build sim.log: sim-run stdin.exe $datadir | ||
bin = stdin.exe | ||
args = +NOTRACE=1 | ||
build stdin.json: json-data $datadir sim.log | json-dat.py | ||
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default stdin.json |
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,48 @@ | ||
--- | ||
source: fud2/tests/tests.rs | ||
description: emit calyx -> vcd through verilator | ||
--- | ||
build-tool = fud2 | ||
rule get-rsrc | ||
command = $build-tool get-rsrc $out | ||
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# Calyx compiler | ||
calyx-base = /test/calyx | ||
calyx-exe = $calyx-base/target/debug/calyx | ||
rule calyx | ||
command = $calyx-exe -l $calyx-base -b $backend $args $in > $out | ||
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||
# RTL simulation | ||
python = python3 | ||
build json-dat.py: get-rsrc | ||
rule hex-data | ||
command = $python json-dat.py --from-json $in $out | ||
rule json-data | ||
command = $python json-dat.py --to-json $out $in | ||
build tb.sv: get-rsrc | ||
sim_data = /test/data.json | ||
datadir = sim_data | ||
build $datadir: hex-data $sim_data | json-dat.py | ||
rule sim-run | ||
command = ./$bin +DATA=$datadir +CYCLE_LIMIT=$cycle-limit $args > $out | ||
cycle-limit = 500000000 | ||
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# Verilator | ||
verilator = verilator | ||
cycle-limit = 500000000 | ||
rule verilator-compile | ||
command = $verilator $in tb.sv --trace --binary --top-module TOP -fno-inline -Mdir $out-dir | ||
rule cp | ||
command = cp $in $out | ||
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# build targets | ||
build stdin.sv: calyx stdin | ||
backend = verilog | ||
build verilator-out/VTOP: verilator-compile stdin.sv | tb.sv | ||
out-dir = verilator-out | ||
build stdin.exe: cp verilator-out/VTOP | ||
build sim.log stdin.vcd: sim-run stdin.exe $datadir | ||
bin = stdin.exe | ||
args = +NOTRACE=0 +OUT=stdin.vcd | ||
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default stdin.vcd |
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@@ -0,0 +1,74 @@ | ||
--- | ||
source: fud2/tests/tests.rs | ||
description: emit calyx -> vcd through xrt-trace | ||
--- | ||
build-tool = fud2 | ||
rule get-rsrc | ||
command = $build-tool get-rsrc $out | ||
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# Calyx compiler | ||
calyx-base = /test/calyx | ||
calyx-exe = $calyx-base/target/debug/calyx | ||
rule calyx | ||
command = $calyx-exe -l $calyx-base -b $backend $args $in > $out | ||
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# Xilinx tools | ||
vivado-dir = /test/xilinx/vivado | ||
vitis-dir = /test/xilinx/vitis | ||
build gen_xo.tcl: get-rsrc | ||
build get-ports.py: get-rsrc | ||
python = python3 | ||
rule gen-xo | ||
command = $vivado-dir/bin/vivado -mode batch -source gen_xo.tcl -tclargs $out `$python get-ports.py kernel.xml` | ||
pool = console | ||
xilinx-mode = hw_emu | ||
platform = xilinx_u50_gen3x16_xdma_201920_3 | ||
rule compile-xclbin | ||
command = $vitis-dir/bin/v++ -g -t $xilinx-mode --platform $platform --save-temps --profile.data all:all:all --profile.exec all:all:all -lo $out $in | ||
pool = console | ||
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# RTL simulation | ||
python = python3 | ||
build json-dat.py: get-rsrc | ||
rule hex-data | ||
command = $python json-dat.py --from-json $in $out | ||
rule json-data | ||
command = $python json-dat.py --to-json $out $in | ||
build tb.sv: get-rsrc | ||
sim_data = /test/data.json | ||
datadir = sim_data | ||
build $datadir: hex-data $sim_data | json-dat.py | ||
rule sim-run | ||
command = ./$bin +DATA=$datadir +CYCLE_LIMIT=$cycle-limit $args > $out | ||
cycle-limit = 500000000 | ||
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# Xilinx execution via XRT | ||
rule emconfig | ||
command = $vitis-dir/bin/emconfigutil --platform $platform | ||
build emconfig.json: emconfig | ||
xrt-dir = /test/xilinx/xrt | ||
rule xclrun | ||
command = bash -c 'source $vitis-dir/settings64.sh ; source $xrt-dir/setup.sh ; XRT_INI_PATH=$xrt_ini EMCONFIG_PATH=. XCL_EMULATION_MODE=$xilinx-mode $python -m fud.xclrun --out $out $in' | ||
pool = console | ||
rule echo | ||
command = echo $contents > $out | ||
build pre_sim.tcl: echo | | ||
contents = open_vcd\\nlog_vcd *\\n | ||
build post_sim.tcl: echo | | ||
contents = close_vcd\\n | ||
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# build targets | ||
build main.sv: calyx stdin | ||
backend = verilog | ||
args = --synthesis -p external | ||
build toplevel.v: calyx stdin | ||
backend = xilinx | ||
build kernel.xml: calyx stdin | ||
backend = xilinx-xml | ||
build stdin.xo: gen-xo | main.sv toplevel.v kernel.xml gen_xo.tcl get-ports.py | ||
build stdin.xclbin: compile-xclbin stdin.xo | ||
build xrt_trace.ini: get-rsrc | ||
build stdin.vcd: xclrun stdin.xclbin $sim_data | emconfig.json pre_sim.tcl post_sim.tcl xrt_trace.ini | ||
xrt_ini = xrt_trace.ini | ||
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default stdin.vcd |
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