[Cider 2.0] random grab bag of stuff (#1778)

* move some of the env stuff

* very rough stab at the next code

* add the missing seq processing

* typo

* rearrange

* checkpoint with semi-functional std memories

* add the stdmem to the primitive builder

* unfinished but i don't wanna stash rn

* some refactoring shennanigans

* flesh out the par portion of the descent

* dubious checkpoint

* remove all the frills from Value

* clippy cleanup

* clippy's wrath

* remove import

* minor cleanup

* sketch of new value construct

* environment is a module now. this code doesn't work

* checkpoint

interp/src/flatten/flat_ir/base.rs

@@ -85,7 +85,9 @@ impl_index!(LocalCellOffset);
 pub struct LocalRefCellOffset(u32);
 impl_index!(LocalRefCellOffset);
 
-/// Enum used in assignments to encapsulate the different types of port references
+/// Enum used in assignments to encapsulate the different types of port
+/// references these are always relative to a component's base-point and must be
+/// converted to global references when used.
 #[derive(Debug, Copy, Clone)]
 pub enum PortRef {
     /// A port belonging to a non-ref cell/group in the current component or the
@@ -135,6 +137,46 @@ impl From<LocalPortOffset> for PortRef {
     }
 }
 
+/// This is the global analogue to [PortRef] and contains global identifiers
+/// after the relative offsets have been transformed via a component base location
+pub enum GlobalPortRef {
+    /// A non-ref port with an exact address
+    Port(GlobalPortId),
+    /// A reference port
+    Ref(GlobalRefPortId),
+}
+
+impl From<GlobalRefPortId> for GlobalPortRef {
+    fn from(v: GlobalRefPortId) -> Self {
+        Self::Ref(v)
+    }
+}
+
+impl From<GlobalPortId> for GlobalPortRef {
+    fn from(v: GlobalPortId) -> Self {
+        Self::Port(v)
+    }
+}
+
+impl GlobalPortRef {
+    #[must_use]
+    pub fn as_port(&self) -> Option<&GlobalPortId> {
+        if let Self::Port(v) = self {
+            Some(v)
+        } else {
+            None
+        }
+    }
+
+    #[must_use]
+    pub fn as_ref(&self) -> Option<&GlobalRefPortId> {
+        if let Self::Ref(v) = self {
+            Some(v)
+        } else {
+            None
+        }
+    }
+}
 /// An enum wrapping the two different types of port definitions (ref/local)
 pub enum PortDefinitionRef {
     Local(PortDefinitionIdx),

interp/src/flatten/flat_ir/control/structures.rs

@@ -5,7 +5,7 @@ use crate::flatten::{
     structures::{index_trait::impl_index, indexed_map::IndexedMap},
 };
 
-#[derive(Debug, Eq, Copy, Clone, PartialEq, Hash)]
+#[derive(Debug, Eq, Copy, Clone, PartialEq, Hash, PartialOrd)]
 pub struct ControlIdx(u32);
 impl_index!(ControlIdx);
 

interp/src/flatten/mod.rs

@@ -5,13 +5,14 @@ pub(crate) mod text_utils;
 
 use structures::environment::Environment;
 
+use self::structures::environment::Simulator;
+
 pub fn flat_main(ctx: &calyx_ir::Context) {
     let i_ctx = flat_ir::control::translator::translate(ctx);
 
     i_ctx.printer().print_program();
 
     let env = Environment::new(&i_ctx);
-    env.print_env_stats();
-    env.print_env();
-    env.print_pc()
+    let mut sim = Simulator::new(env);
+    sim._main_test()
 }

interp/src/flatten/primitives/builder.rs

@@ -1,16 +1,16 @@
 use crate::{
     flatten::{
         flat_ir::{
-            cell_prototype::{CellPrototype, PrimType1},
+            cell_prototype::{CellPrototype, MemType, PrimType1},
             prelude::{CellInfo, GlobalPortId},
         },
         structures::environment::Environment,
     },
     values::Value,
 };
 
-use super::stateful::*;
 use super::{combinational::*, Primitive};
+use super::{prim_trait::DummyPrimitive, stateful::*};
 
 pub fn build_primitive(
     env: &mut Environment,
@@ -59,7 +59,7 @@ pub fn build_primitive(
             PrimType1::SignedLe => Box::new(StdSle::new(base_port)),
             PrimType1::SignedLsh => Box::new(StdSlsh::new(base_port)),
             PrimType1::SignedRsh => Box::new(StdSrsh::new(base_port)),
-            PrimType1::MultPipe => todo!(),
+            PrimType1::MultPipe => Box::new(DummyPrimitive),
             PrimType1::SignedMultPipe => todo!(),
             PrimType1::DivPipe => todo!(),
             PrimType1::SignedDivPipe => todo!(),
@@ -103,41 +103,53 @@ pub fn build_primitive(
             out: _,
         } => todo!(),
         CellPrototype::MemD1 {
-            mem_type: _,
-            width: _,
-            size: _,
+            mem_type,
+            width,
+            size,
             idx_size: _,
-        } => todo!(),
+        } => match mem_type {
+            MemType::Seq => todo!("SeqMem primitives are not currently defined in the flat interpreter"),
+            MemType::Std => Box::new(StdMemD1::new(base_port, *width, false, *size as usize))
+        },
         CellPrototype::MemD2 {
-            mem_type: _,
-            width: _,
-            d0_size: _,
-            d1_size: _,
+            mem_type,
+            width,
+            d0_size,
+            d1_size,
             d0_idx_size: _,
             d1_idx_size: _,
-        } => todo!(),
+        } => match mem_type {
+            MemType::Seq => todo!("SeqMem primitives are not currently defined in the flat interpreter"),
+            MemType::Std => Box::new(StdMemD2::new(base_port, *width, false, (*d0_size as usize, *d1_size as usize))),
+        },
         CellPrototype::MemD3 {
-            mem_type: _,
-            width: _,
-            d0_size: _,
-            d1_size: _,
-            d2_size: _,
+            mem_type,
+            width,
+            d0_size,
+            d1_size,
+            d2_size,
             d0_idx_size: _,
             d1_idx_size: _,
             d2_idx_size: _,
-        } => todo!(),
+        }  => match mem_type {
+            MemType::Seq => todo!("SeqMem primitives are not currently defined in the flat interpreter"),
+            MemType::Std => Box::new(StdMemD3::new(base_port, *width, false, (*d0_size as usize, *d1_size as usize, *d2_size as usize))),
+        },
         CellPrototype::MemD4 {
-            mem_type: _,
-            width: _,
-            d0_size: _,
-            d1_size: _,
-            d2_size: _,
-            d3_size: _,
+            mem_type,
+            width,
+            d0_size,
+            d1_size,
+            d2_size,
+            d3_size,
             d0_idx_size: _,
             d1_idx_size: _,
             d2_idx_size: _,
             d3_idx_size: _,
-        } => todo!(),
+        }=> match mem_type {
+            MemType::Seq => todo!("SeqMem primitives are not currently defined in the flat interpreter"),
+            MemType::Std => Box::new(StdMemD4::new(base_port, *width, false, (*d0_size as usize, *d1_size as usize, *d2_size as usize, *d3_size as usize))),
+        },
         CellPrototype::Unknown(_, _) => todo!(),
     }
 }

interp/src/flatten/primitives/macros.rs

@@ -20,7 +20,20 @@ macro_rules! output {
     }
 }
 
+macro_rules! make_getters {
+    ($base:ident; $( $port:ident : $offset:expr ),+ ) => {
+        $(
+            #[inline]
+            fn $port(&self) -> $crate::flatten::flat_ir::prelude::GlobalPortId {
+                ($crate::flatten::structures::index_trait::IndexRef::index(&self.$base) + $offset).into()
+            }
+        )+
+
+    }
+}
+
 pub(crate) use declare_ports;
+pub(crate) use make_getters;
 pub(crate) use output;
 pub(crate) use ports;
 

interp/src/flatten/primitives/stateful/math.rs

@@ -0,0 +1 @@
+