Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Fix RPT extraction on older targets #2356

Open
wants to merge 2 commits into
base: main
Choose a base branch
from
Open

Fix RPT extraction on older targets #2356

Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
6c8f6b4
Update extraction for older targets
UnsignedByte Nov 19, 2024
471cf9a
Merge branch 'main' into main
UnsignedByte Nov 19, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
41 changes: 27 additions & 14 deletions fud/fud/stages/vivado/extract.py
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -79,22 +79,35 @@ def place_and_route_extract(
try:
if util_file.exists():
impl_parser = rpt.RPTParser(util_file)
slice_logic = impl_parser.get_table(re.compile(r"1\. CLB Logic"), 2)
dsp_table = impl_parser.get_table(re.compile(r"4\. ARITHMETIC"), 2)

clb_lut = to_int(find_row(slice_logic, "Site Type", "CLB LUTs")["Used"])
clb_reg = to_int(
find_row(slice_logic, "Site Type", "CLB Registers")["Used"]
)
carry8 = to_int(find_row(slice_logic, "Site Type", "CARRY8")["Used"])
f7_muxes = to_int(find_row(slice_logic, "Site Type", "F7 Muxes")["Used"])
f8_muxes = to_int(find_row(slice_logic, "Site Type", "F8 Muxes")["Used"])
f9_muxes = to_int(find_row(slice_logic, "Site Type", "F9 Muxes")["Used"])
try:
slice_logic = impl_parser.get_table(re.compile(r"1\. CLB Logic"), 2)
dsp_table = impl_parser.get_table(re.compile(r"4\. ARITHMETIC"), 2)

clb_lut = to_int(find_row(slice_logic, "Site Type", "CLB LUTs")["Used"])
clb_reg = to_int(
find_row(slice_logic, "Site Type", "CLB Registers")["Used"]
)
carry8 = to_int(find_row(slice_logic, "Site Type", "CARRY8")["Used"])
f7_muxes = to_int(find_row(slice_logic, "Site Type", "F7 Muxes")["Used"])
f8_muxes = to_int(find_row(slice_logic, "Site Type", "F8 Muxes")["Used"])
f9_muxes = to_int(find_row(slice_logic, "Site Type", "F9 Muxes")["Used"])
except:
# Older FPGAs use a different table format
slice_logic = impl_parser.get_table(re.compile(r"1\. Slice Logic"), 2)
dsp_table = impl_parser.get_table(re.compile(r"4\. DSP"), 2)
clb_lut = to_int(find_row(slice_logic, "Site Type", "Slice LUTs")["Used"])
clb_reg = to_int(
find_row(slice_logic, "Site Type", "Slice Registers")["Used"]
)
carry8 = -1
f7_muxes = to_int(find_row(slice_logic, "Site Type", "F7 Muxes")["Used"])
f8_muxes = to_int(find_row(slice_logic, "Site Type", "F8 Muxes")["Used"])
f9_muxes = -1


resource_info.update(
{
"lut": to_int(
find_row(slice_logic, "Site Type", "CLB LUTs")["Used"]
),
"lut": clb_lut,
"dsp": to_int(find_row(dsp_table, "Site Type", "DSPs")["Used"]),
"registers": rtl_component_extract(synth_file, "Registers"),
"muxes": rtl_component_extract(synth_file, "Muxes"),
Expand Down
Loading