🎨 Improved usability of the on-the-fly SiDB gate library

bindings/mnt/pyfiction/include/pyfiction/layouts/cell_level_layout.hpp

@@ -124,6 +124,11 @@ void fcn_technology_cell_level_layout(pybind11::module& m)
         .def("is_pi", &py_cartesian_technology_cell_layout::is_pi, py::arg("c"), DOC(fiction_cell_level_layout_is_pi))
         .def("is_po", &py_cartesian_technology_cell_layout::is_po, py::arg("c"), DOC(fiction_cell_level_layout_is_po))
 
+        // todo add docu
+        .def("get_cell_type", &py_cartesian_technology_cell_layout::get_cell_type, py::arg("c"))
+        .def("get_cells_by_type", &py_cartesian_technology_cell_layout::get_cells_by_type, py::arg("type"))
+        .def("num_cells_of_given_type", &py_cartesian_technology_cell_layout::num_cells_of_given_type, py::arg("type"))
+
         .def("cells",
              [](const py_cartesian_technology_cell_layout& lyt)
              {

bindings/mnt/pyfiction/include/pyfiction/technology/sidb_lattice.hpp

@@ -32,7 +32,6 @@ template <typename LatticeOrientation>
 void sidb_lattice_cell_level_layout(pybind11::module& m)
 {
     namespace py = pybind11;
-    namespace py = pybind11;
 
     // fetch technology name
     auto orientation = std::string{fiction::sidb_lattice_name<LatticeOrientation>};

bindings/mnt/pyfiction/test/layouts/test_cell_level_layout.py

@@ -67,6 +67,9 @@ def test_cell_type_assignment(self):
         layout.assign_cell_type((3, 2), qca_technology.cell_type.NORMAL)
         layout.assign_cell_type((4, 2), qca_technology.cell_type.OUTPUT)
 
+        self.assertEqual(layout.get_cells_by_type(qca_technology.cell_type.OUTPUT), [(4, 2)])
+        self.assertEqual(layout.num_cells_of_given_type(qca_technology.cell_type.INPUT), 2)
+
         self.assertFalse(layout.is_empty())
 
         layout.assign_cell_name((0, 2), "a")

experiments/physical_design_with_on_the_fly_gate_design/on_the_fly_sidb_circuit_design_on_defective_surface.cpp

@@ -146,7 +146,7 @@ int main()  // NOLINT
         params.exact_design_parameters.upper_bound_y = 30;         // 12 x 31 tiles
         params.exact_design_parameters.timeout       = 3'600'000;  // 1h in ms
 
-        params.sidb_on_the_fly_gate_library_parameters.defect_surface     = std::optional{surface_lattice};
+        params.sidb_on_the_fly_gate_library_parameters.defect_surface     = surface_lattice;
         params.sidb_on_the_fly_gate_library_parameters.design_gate_params = design_gate_params;
 
         fiction::on_the_fly_circuit_design_on_defective_surface_stats<gate_lyt> st{};

include/fiction/algorithms/physical_design/on_the_fly_sidb_circuit_design.hpp

@@ -21,11 +21,28 @@
 #include <cstdio>
 #include <optional>
 #include <stdexcept>
+#include <string_view>
 #include <utility>
 
 namespace fiction
 {
 
+/**
+ * Exception thrown when no valid placement and routing is found for the given blacklist.
+ */
+class unsuccessful_pr_error : public std::runtime_error
+{
+  public:
+    explicit unsuccessful_pr_error(const std::string_view& msg) noexcept : std::runtime_error(msg.data()) {}
+};
+/**
+ * Exception thrown when the gate design was unsuccessful.
+ */
+class unsuccessful_gate_design_error : public std::runtime_error
+{
+  public:
+    explicit unsuccessful_gate_design_error(const std::string_view& msg) noexcept : std::runtime_error(msg.data()) {}
+};
 /**
  * This struct stores the parameters to design an SiDB circuit on a defective surface.
  *
@@ -101,7 +118,7 @@ struct on_the_fly_circuit_design_on_defective_surface_stats
  * @param defective_surface The defective surface on which the SiDB circuit is designed.
  * @param params The parameters used for designing the circuit, encapsulated in an
  * `on_the_fly_sidb_circuit_design_params` object.
- * @param stats Pointer to a structure for collecting statistics. If nullptr, statistics are not collected.
+ * @param stats Pointer to a structure for collecting statistics. If `nullptr`, statistics are discarded.
  * @return A `sidb_defect_surface<CellLyt>` representing the designed circuit on the defective surface.
  */
 template <typename Ntk, typename CellLyt, typename GateLyt>
@@ -171,20 +188,30 @@ template <typename Ntk, typename CellLyt, typename GateLyt>
                     fmt::print(stderr, "[e] Terminating loop due to critical error.\n");
                     break;
                 }
+
+                catch (...)
+                {
+                    fmt::print(stderr, "[e] An unexpected error occurred during gate design.\n");
+                    fmt::print(stderr, "[e] Terminating loop due to critical error.\n");
+                    break;
+                }
             }
             // P&R was unsuccessful
             else
             {
-                throw std::runtime_error("P&R was unsuccessful");
+                throw unsuccessful_pr_error("Placement and routing was unsuccessful");
             }
         }
 
         sidb_defect_surface<CellLyt> sidbs_and_defects{lyt};
 
-        // add defects to the circuit.
-        params.sidb_on_the_fly_gate_library_parameters.defect_surface.value().foreach_sidb_defect(
-            [&sidbs_and_defects](const auto& defect)
-            { sidbs_and_defects.assign_sidb_defect(defect.first, defect.second); });
+        if (params.sidb_on_the_fly_gate_library_parameters.defect_surface.has_value())
+        {
+            // add defects to the circuit.
+            params.sidb_on_the_fly_gate_library_parameters.defect_surface.value().foreach_sidb_defect(
+                [&sidbs_and_defects](const auto& defect)
+                { sidbs_and_defects.assign_sidb_defect(defect.first, defect.second); });
+        }
 
         result = sidbs_and_defects;
     }
@@ -209,7 +236,7 @@ template <typename Ntk, typename CellLyt, typename GateLyt>
  * @param lattice_tiling The lattice tiling used for the circuit design.
  * @param params The parameters used for designing the circuit, encapsulated in an
  * `on_the_fly_sidb_circuit_design_params` object.
- * @param stats Pointer to a structure for collecting statistics. If `nullptr`, statistics are not collected.
+ * @param stats Pointer to a structure for collecting statistics. If `nullptr`, statistics are discarded.
  * @return A `CellLyt` representing the designed SiDB circuit.
  */
 template <typename CellLyt, typename GateLyt>
@@ -234,7 +261,7 @@ template <typename CellLyt, typename GateLyt>
     // blacklist and the process is rerun.
     catch (const gate_design_exception<tt, GateLyt>& e)
     {
-        throw std::runtime_error("Gate design was unsuccessful");
+        throw unsuccessful_gate_design_error("Gate design was unsuccessful");
     }
 }
 

include/fiction/technology/fcn_gate_library.hpp

@@ -38,7 +38,7 @@ class unsupported_gate_type_exception : public std::exception
 
   private:
     /**
-     * Coordinate of teh layout where the unsupported gate type was found.
+     * Coordinate at which the unsupported gate type was found.
      */
     const CoordinateType coord;
 };
@@ -59,14 +59,18 @@ class unsupported_gate_orientation_exception : public std::exception
             ports{p}
     {}
     /**
-     * Coordinate of the layout where the unsupported gate orientation was found.
+     * Coordinate at which the unsupported gate orientation was found.
+     *
+     * @return Coordinate.
      */
     [[nodiscard]] CoordinateType where() const noexcept
     {
         return coord;
     }
     /**
      * Ports of the unsupported gate orientation.
+     *
+     * @return Ports.
      */
     [[nodiscard]] port_list<PortType> which_ports() const noexcept
     {
@@ -75,7 +79,7 @@ class unsupported_gate_orientation_exception : public std::exception
 
   private:
     /**
-     * Coordinate of the layout where the unsupported gate orientation was found.
+     * Coordinate at which the unsupported gate orientation was found.
      */
     const CoordinateType coord;
     /**

include/fiction/technology/sidb_defect_surface.hpp

@@ -11,6 +11,7 @@
 #include <phmap.h>
 
 #include <cassert>
+#include <cstddef>
 #include <cstdint>
 #include <memory>
 #include <optional>
@@ -184,24 +185,43 @@ class sidb_defect_surface<Lyt, false> : public Lyt
         return strg->defective_coordinates.size();
     }
     /**
-     * Returns the number of charged defects.
      *
-     * @return Number of charged defects.
      */
-    [[nodiscard]] std::size_t num_charged_defects() const noexcept
+    [[nodiscard]] std::size_t num_positively_charged_defects() const noexcept
     {
-        std::size_t number_of_charged_defects = 0;
+        std::size_t number_of_positively_charged_defects = 0;
 
         this->foreach_sidb_defect(
-            [&number_of_charged_defects](const auto& defect)
+            [&number_of_positively_charged_defects](const auto& defect)
             {
-                if (is_charged_defect_type(defect.second))
+                if (is_positively_charged_defect(defect.second))
                 {
-                    number_of_charged_defects++;
+                    number_of_positively_charged_defects++;
                 }
             });
 
-        return number_of_charged_defects;
+        return number_of_positively_charged_defects;
+    }
+
+    [[nodiscard]] std::size_t num_negatively_charged_defects() const noexcept
+    {
+        std::size_t number_of_negatively_charged_defects = 0;
+
+        this->foreach_sidb_defect(
+            [&number_of_negatively_charged_defects](const auto& defect)
+            {
+                if (is_negatively_charged_defect(defect.second))
+                {
+                    number_of_negatively_charged_defects++;
+                }
+            });
+
+        return number_of_negatively_charged_defects;
+    }
+
+    [[nodiscard]] std::size_t num_charged_defects() const noexcept
+    {
+        return num_positively_charged_defects() + num_negatively_charged_defects();
     }
     /**
      * Returns the number of neutral defects.

include/fiction/technology/sidb_on_the_fly_gate_library.hpp

@@ -138,7 +138,7 @@ struct sidb_on_the_fly_gate_library_params
      */
     double influence_radius_charged_defects = 15;  // (unit: nm)
     /**
-     * This layout stores all atomic defects. ``std::nullopt`` if no defect surface is given.
+     * This layout stores all atomic defects. `std::nullopt` if no defect surface is given.
      */
     std::optional<sidb_defect_surface<Lyt>> defect_surface{std::nullopt};
 };
@@ -234,7 +234,7 @@ class sidb_on_the_fly_gate_library : public fcn_gate_library<sidb_technology, 60
                                         defect_surface.value(), skeleton, params.influence_radius_charged_defects,
                                         center_cell, absolute_cell);
 
-                                    if (is_bestagon_gate_applicable(
+                                    if (is_predefined_bestagon_gate_applicable(
                                             cell_list_to_cell_level_layout<CellLyt>(DOUBLE_WIRE), skeleton_with_defects,
                                             create_double_wire_tt(), params))
                                     {
@@ -261,9 +261,9 @@ class sidb_on_the_fly_gate_library : public fcn_gate_library<sidb_technology, 60
                                     defect_surface.value(), skeleton, params.influence_radius_charged_defects,
                                     center_cell, absolute_cell);
 
-                                if (is_bestagon_gate_applicable(cell_list_to_cell_level_layout<CellLyt>(CROSSING),
-                                                                skeleton_with_defects, create_crossing_wire_tt(),
-                                                                params))
+                                if (is_predefined_bestagon_gate_applicable(
+                                        cell_list_to_cell_level_layout<CellLyt>(CROSSING), skeleton_with_defects,
+                                        create_crossing_wire_tt(), params))
                                 {
                                     return CROSSING;
                                 }
@@ -525,23 +525,23 @@ class sidb_on_the_fly_gate_library : public fcn_gate_library<sidb_technology, 60
 
   private:
     /**
-     * This function evaluates whether a Bestagon gate can be applied to the given node by considering
+     * This function evaluates whether a predefined Bestagon gate can be applied to the given node by considering
      * various conditions, including the presence of defects and spacing requirements.
      *
      * @tparam Lyt The type of the cell-level layout.
      * @tparam TT Truth table type.
      * @tparam Params Type of the parameters used for the parametrized gate library.
      * @param bestagon_lyt The Bestagon gate which is to be applied.
+     * @param skeleton_with_defects The skeleton layout with atomic defects.
      * @param truth_table The truth table representing the gate's logic function.
      * @param parameters Parameters for the gate design and simulation.
      * @return `true` if the Bestagon gate is applicable to the layout, considering the provided conditions;
      *         otherwise, returns `false`.
      */
     template <typename Lyt, typename TT>
-    [[nodiscard]] static bool is_bestagon_gate_applicable(const Lyt&                      bestagon_lyt,
-                                                          const sidb_defect_surface<Lyt>& skeleton_with_defects,
-                                                          const std::vector<TT>&          truth_table,
-                                                          const sidb_on_the_fly_gate_library_params<Lyt>& parameters)
+    [[nodiscard]] static bool is_predefined_bestagon_gate_applicable(
+        const Lyt& bestagon_lyt, const sidb_defect_surface<Lyt>& skeleton_with_defects,
+        const std::vector<TT>& truth_table, const sidb_on_the_fly_gate_library_params<Lyt>& parameters)
     {
         const auto sidbs_affected_by_defects = skeleton_with_defects.all_affected_sidbs(std::pair(0, 0));
 
@@ -551,12 +551,10 @@ class sidb_on_the_fly_gate_library : public fcn_gate_library<sidb_technology, 60
 
         assert(!logic_cells.empty() && "No Logic cells are found");
 
-        for (const auto& l_cells : logic_cells)
+        if (std::any_of(logic_cells.cbegin(), logic_cells.cend(),
+                        [&](const auto& l_cell) { return sidbs_affected_by_defects.count(l_cell); }))
         {
-            if (sidbs_affected_by_defects.count(l_cells))
-            {
-                return false;
-            }
+            return false;
         }
 
         for (const auto& l_cells : logic_cells)