Collective PR to combine tests increasing coverage #238

wsipak · 2024-10-01T12:12:30Z

This PR combines changes from:

github-actions · 2024-10-03T21:51:20Z

Links to coverage and verification reports for this PR (#238) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

github-actions · 2024-10-04T13:37:40Z

Links to coverage and verification reports for this PR (#238) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

github-actions · 2024-10-04T14:01:03Z

design/lib/ahb_to_axi4.sv

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

endmodule // ahb_to_axi4

endmodule // ahb_to_axi4

github-actions · 2024-10-04T16:54:38Z

Links to coverage and verification reports for this PR (#238) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

github-actions · 2024-10-04T18:12:24Z

Links to coverage and verification reports for this PR (#238) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

github-actions · 2024-10-04T19:27:53Z

Links to coverage and verification reports for this PR (#238) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

github-actions · 2024-10-06T15:19:41Z

design/el2_veer_wrapper.sv

@@ -418,6 +490,8 @@ import el2_pkg::*;

   // zero out the signals not presented at the wrapper instantiation level


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

// zero out the signals not presented at the wrapper instantiation level

// zero out the signals not presented at the wrapper instantiation level

github-actions · 2024-10-06T19:26:29Z

Links to coverage and verification reports for this PR (#238) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

github-actions · 2024-10-06T19:42:46Z

design/el2_veer_wrapper.sv

+
+   /*verilator coverage_on*/


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]

Suggested change

/*verilator coverage_on*/

/*verilator coverage_on*/

github-actions · 2024-10-06T23:13:52Z

Links to coverage and verification reports for this PR (#238) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

github-actions · 2024-10-07T15:12:10Z

Links to coverage and verification reports for this PR (#238) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

github-actions · 2024-10-07T18:12:07Z

Links to coverage and verification reports for this PR (#238) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

github-actions · 2024-10-07T23:13:08Z

Links to coverage and verification reports for this PR (#238) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

github-actions · 2024-10-08T12:07:55Z

Links to coverage and verification reports for this PR (#238) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

github-actions · 2024-10-08T17:44:06Z

Links to coverage and verification reports for this PR (#238) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

github-actions · 2024-10-09T15:11:30Z

Links to coverage and verification reports for this PR (#238) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

github-actions · 2024-10-09T21:57:49Z

design/el2_pmp.sv

    input logic scan_mode, // Scan mode
+    /* verilator coverage_on */

 `ifdef RV_SMEPMP
    input el2_mseccfg_pkt_t mseccfg, // mseccfg CSR content, RLB, MMWP and MML bits


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

input el2_mseccfg_pkt_t mseccfg, // mseccfg CSR content, RLB, MMWP and MML bits

input el2_mseccfg_pkt_t mseccfg, // mseccfg CSR content, RLB, MMWP and MML bits

github-actions · 2024-10-09T21:57:49Z

design/el2_pmp.sv

        2'b11: result =
             (pmp_req_type == EXEC) |
            ((pmp_req_type == READ) & ~priv_mode);


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

2'b11: result =

(pmp_req_type == EXEC) |

((pmp_req_type == READ) & ~priv_mode);

2'b11: result = (pmp_req_type == EXEC) | ((pmp_req_type == READ) & ~priv_mode);

github-actions · 2024-10-10T07:00:37Z

Links to coverage and verification reports for this PR (#238) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

github-actions · 2024-10-10T17:31:09Z

design/ifu/el2_ifu_mem_ctl.sv

         end
+         /*verilator coverage_on*/
      endcase
   end
   rvdffs #(($bits(err_stop_state_t))) err_stop_state_ff (.clk(active_clk), .din(err_stop_nxtstate), .dout({err_stop_state}), .en(err_stop_state_en),   .*);


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

end

/*verilator coverage_on*/

endcase

end

rvdffs #(($bits(err_stop_state_t))) err_stop_state_ff (.clk(active_clk), .din(err_stop_nxtstate), .dout({err_stop_state}), .en(err_stop_state_en), .*);

end

/*verilator coverage_on*/

endcase

end

rvdffs #(($bits(

err_stop_state_t

))) err_stop_state_ff (

.clk (active_clk),

.din (err_stop_nxtstate),

.dout({err_stop_state}),

.en (err_stop_state_en),

.*

);

github-actions · 2024-10-11T10:55:34Z

Links to coverage and verification reports for this PR (#238) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

github-actions · 2024-10-11T15:32:10Z

Links to coverage and verification reports for this PR (#238) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

Signed-off-by: Wojciech Sipak <[email protected]>

Signed-off-by: Karol Gugala <[email protected]>

Signed-off-by: Krzysztof Obłonczek <[email protected]> Co-authored-by: Karol Gugala <[email protected]>

This way matrix size is below 256 Also limit exceptions tests to AXI and M mode Signed-off-by: Karol Gugala <[email protected]> Co-authored-by: Wojciech Sipak <[email protected]>

Signed-off-by: Wojciech Sipak <[email protected]> Co-authored-by: Karol Gugala <[email protected]> Co-authored-by: Tomasz Michalak <[email protected]> Co-authored-by: Robert Szczepanski <[email protected]>

Signed-off-by: Karol Gugala <[email protected]>

Signed-off-by: Wojciech Sipak <[email protected]>

Signed-off-by: Tomasz Michalak <[email protected]>

Signed-off-by: Robert Szczepanski <[email protected]>

wsipak force-pushed the wsip/debug_coverage branch 7 times, most recently from d63c76d to 8faf6d0 Compare October 3, 2024 17:55

github-actions bot reviewed Oct 4, 2024

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github-actions bot reviewed Oct 6, 2024

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wsipak force-pushed the wsip/debug_coverage branch from 37380d2 to 07c55eb Compare October 9, 2024 07:42

tmichalak force-pushed the wsip/debug_coverage branch from 07c55eb to 4be86d0 Compare October 9, 2024 09:06

github-actions bot reviewed Oct 9, 2024

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github-actions bot reviewed Oct 10, 2024

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docs: Pin Sphinx to 8.0.2

e6e2ec6

update ci to use docker image

b372844

wsipak changed the title ~~test the debug module with GDB~~ Collective PR to combine tests increasing coverage Oct 11, 2024

wsipak force-pushed the wsip/debug_coverage branch from 6107ef2 to c564971 Compare October 11, 2024 15:31

wsipak and others added 3 commits October 11, 2024 17:32

test the debug module with GDB

e1ef54f

Signed-off-by: Wojciech Sipak <[email protected]>

verif: add no-table flags to all the tests

f476e33

Signed-off-by: Karol Gugala <[email protected]>

Add tests for exceptions

bd93c80

Signed-off-by: Krzysztof Obłonczek <[email protected]> Co-authored-by: Karol Gugala <[email protected]>

wsipak force-pushed the wsip/debug_coverage branch from c564971 to ddf4406 Compare October 11, 2024 15:32

tmichalak mentioned this pull request Oct 11, 2024

WIP: Increase coverage #243

Closed

wsipak force-pushed the wsip/debug_coverage branch from ddf4406 to 0a85856 Compare October 11, 2024 15:44

kgugala and others added 6 commits October 11, 2024 17:59

CI: split regression tests into two flows

344e6ae

This way matrix size is below 256 Also limit exceptions tests to AXI and M mode Signed-off-by: Karol Gugala <[email protected]> Co-authored-by: Wojciech Sipak <[email protected]>

exclude signals tied to const values from coverage

83f4a8e

Signed-off-by: Wojciech Sipak <[email protected]> Co-authored-by: Karol Gugala <[email protected]> Co-authored-by: Tomasz Michalak <[email protected]> Co-authored-by: Robert Szczepanski <[email protected]>

verlator: testbench: test CPU halt and restart

70cd4d9

Signed-off-by: Karol Gugala <[email protected]>

add tests for custom CSRs

b292525

Signed-off-by: Wojciech Sipak <[email protected]>

Increase coverage of pmp permission tests

e0cc7d1

Signed-off-by: Tomasz Michalak <[email protected]>

Remove unused signal

b7d2856

Signed-off-by: Robert Szczepanski <[email protected]>

wsipak force-pushed the wsip/debug_coverage branch from 0a85856 to b7d2856 Compare October 11, 2024 16:03

This was referenced Oct 11, 2024

1: Test with gdb #244

Closed

2: Test exceptions #241

Closed

wsipak marked this pull request as ready for review October 11, 2024 16:21

tmichalak merged commit 199eae1 into main Oct 11, 2024
571 of 575 checks passed

wsipak deleted the wsip/debug_coverage branch November 14, 2024 10:28

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Collective PR to combine tests increasing coverage #238

Collective PR to combine tests increasing coverage #238

wsipak commented Oct 1, 2024 •

edited

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github-actions bot commented Oct 11, 2024

		@@ -418,6 +490,8 @@ import el2_pkg::*;

		// zero out the signals not presented at the wrapper instantiation level

	input el2_mseccfg_pkt_t mseccfg, // mseccfg CSR content, RLB, MMWP and MML bits
	input el2_mseccfg_pkt_t mseccfg, // mseccfg CSR content, RLB, MMWP and MML bits

Collective PR to combine tests increasing coverage #238

Collective PR to combine tests increasing coverage #238

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wsipak commented Oct 1, 2024 •

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