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Rename Element to HierarchicalElement
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jerryz123 committed Sep 19, 2023

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1 parent 2c2c168 commit f66de6a
Showing 13 changed files with 71 additions and 71 deletions.
2 changes: 1 addition & 1 deletion src/main/scala/devices/tilelink/BootROM.scala
Original file line number Diff line number Diff line change
@@ -66,7 +66,7 @@ object BootROM {
* at a configurable location, but also drives the tiles' reset vectors to point
* at its 'hang' address parameter value.
*/
def attach(params: BootROMParams, subsystem: BaseSubsystem with HasElements with HasTileInputConstants, where: TLBusWrapperLocation)
def attach(params: BootROMParams, subsystem: BaseSubsystem with HasHierarchicalElements with HasTileInputConstants, where: TLBusWrapperLocation)
(implicit p: Parameters): TLROM = {
val tlbus = subsystem.locateTLBusWrapper(where)
val bootROMDomainWrapper = LazyModule(new ClockSinkDomain(take = None))
6 changes: 3 additions & 3 deletions src/main/scala/groundtest/GroundTestSubsystem.scala
Original file line number Diff line number Diff line change
@@ -14,9 +14,9 @@ import freechips.rocketchip.interrupts.{NullIntSyncSource}

class GroundTestSubsystem(implicit p: Parameters)
extends BaseSubsystem
with InstantiatesElements
with HasElementsRootContext
with HasElements
with InstantiatesHierarchicalElements
with HasHierarchicalElementsRootContext
with HasHierarchicalElements
with HasTileNotificationSinks
with HasTileInputConstants
with CanHaveMasterAXI4MemPort
8 changes: 4 additions & 4 deletions src/main/scala/groundtest/TraceGen.scala
Original file line number Diff line number Diff line change
@@ -26,7 +26,7 @@ import freechips.rocketchip.diplomacy.{ClockCrossingType}
import freechips.rocketchip.rocket._
import freechips.rocketchip.tile._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.subsystem.{ElementCrossingParamsLike, CanAttachTile}
import freechips.rocketchip.subsystem.{HierarchicalElementCrossingParamsLike, CanAttachTile}
import freechips.rocketchip.util._
import freechips.rocketchip.prci.{ClockSinkParameters}

@@ -71,7 +71,7 @@ case class TraceGenParams(
tileId: Int = 0
) extends InstantiableTileParams[TraceGenTile] with GroundTestTileParams
{
def instantiate(crossing: ElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): TraceGenTile = {
def instantiate(crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): TraceGenTile = {
new TraceGenTile(this, crossing, lookup)
}
val blockerCtrlAddr = None
@@ -105,7 +105,7 @@ trait HasTraceGenParams {

case class TraceGenTileAttachParams(
tileParams: TraceGenParams,
crossingParams: ElementCrossingParamsLike
crossingParams: HierarchicalElementCrossingParamsLike
) extends CanAttachTile {
type TileType = TraceGenTile
val lookup: LookupByHartIdImpl = HartsWontDeduplicate(tileParams)
@@ -617,7 +617,7 @@ class TraceGenTile private(
q: Parameters
) extends GroundTestTile(params, crossing, lookup, q)
{
def this(params: TraceGenParams, crossing: ElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters) =
def this(params: TraceGenParams, crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters) =
this(params, crossing.crossingType, lookup, p)

val masterNode: TLOutwardNode = TLIdentityNode() := visibilityNode := dcacheOpt.map(_.node).getOrElse(TLTempNode())
22 changes: 11 additions & 11 deletions src/main/scala/subsystem/Cluster.scala
Original file line number Diff line number Diff line change
@@ -20,22 +20,22 @@ case class ClustersLocated(loc: HierarchicalLocation) extends Field[Seq[CanAttac
case class ClusterParams(
val clusterId: Int,
val clockSinkParams: ClockSinkParameters = ClockSinkParameters()
) extends ElementParams {
) extends HierarchicalElementParams {
val baseName = "cluster"
val uniqueName = s"${baseName}_$clusterId"
def instantiate(crossing: ElementCrossingParamsLike, lookup: LookupByClusterIdImpl)(implicit p: Parameters): Cluster = {
def instantiate(crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByClusterIdImpl)(implicit p: Parameters): Cluster = {
new Cluster(this, crossing.crossingType, lookup)
}
}

class Cluster(
val thisClusterParams: ClusterParams,
crossing: ClockCrossingType,
lookup: LookupByClusterIdImpl)(implicit p: Parameters) extends BaseElement(crossing)(p)
lookup: LookupByClusterIdImpl)(implicit p: Parameters) extends BaseHierarchicalElement(crossing)(p)
with Attachable
with HasConfigurableTLNetworkTopology
with InstantiatesElements
with HasElements
with InstantiatesHierarchicalElements
with HasHierarchicalElements
{
val busContextName = thisClusterParams.baseName
lazy val clusterId = thisClusterParams.clusterId
@@ -78,16 +78,16 @@ class Cluster(
override lazy val module = new ClusterModuleImp(this)
}

class ClusterModuleImp(outer: Cluster) extends BaseElementModuleImp[Cluster](outer)
class ClusterModuleImp(outer: Cluster) extends BaseHierarchicalElementModuleImp[Cluster](outer)

case class InCluster(id: Int) extends HierarchicalLocation(s"Cluster$id")

class ClusterPRCIDomain(
clockSinkParams: ClockSinkParameters,
crossingParams: ElementCrossingParamsLike,
crossingParams: HierarchicalElementCrossingParamsLike,
clusterParams: ClusterParams,
lookup: LookupByClusterIdImpl)
(implicit p: Parameters) extends ElementPRCIDomain[Cluster](clockSinkParams, crossingParams)
(implicit p: Parameters) extends HierarchicalElementPRCIDomain[Cluster](clockSinkParams, crossingParams)
{
val element = element_reset_domain {
LazyModule(clusterParams.instantiate(crossingParams, lookup))
@@ -98,10 +98,10 @@ class ClusterPRCIDomain(


trait CanAttachCluster {
type ClusterContextType <: DefaultElementContextType
type ClusterContextType <: DefaultHierarchicalElementContextType

def clusterParams: ClusterParams
def crossingParams: ElementCrossingParamsLike
def crossingParams: HierarchicalElementCrossingParamsLike

def instantiate(allClusterParams: Seq[ClusterParams], instantiatedClusters: ListMap[Int, ClusterPRCIDomain])(implicit p: Parameters): ClusterPRCIDomain = {
val clockSinkParams = clusterParams.clockSinkParams.copy(name = Some(clusterParams.uniqueName))
@@ -208,7 +208,7 @@ trait CanAttachCluster {

case class ClusterAttachParams(
clusterParams: ClusterParams,
crossingParams: ElementCrossingParamsLike
crossingParams: HierarchicalElementCrossingParamsLike
) extends CanAttachCluster

case class CloneClusterAttachParams(
4 changes: 2 additions & 2 deletions src/main/scala/subsystem/Configs.scala
Original file line number Diff line number Diff line change
@@ -214,7 +214,7 @@ class With1TinyCore extends Config((site, here, up) => {
tiny,
RocketCrossingParams(
crossingType = SynchronousCrossing(),
master = ElementMasterPortParams())
master = HierarchicalElementMasterPortParams())
))
}
case NumTiles => 1
@@ -320,7 +320,7 @@ class WithIncoherentTiles extends Config((site, here, up) => {
case TilesLocated(location) => up(TilesLocated(location), site) map {
case tp: RocketTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
master = tp.crossingParams.master match {
case x: ElementMasterPortParams => x.copy(cork = Some(true))
case x: HierarchicalElementMasterPortParams => x.copy(cork = Some(true))
case _ => throw new Exception("Unrecognized type for RocketCrossingParams.master")
}))
case t => t
Original file line number Diff line number Diff line change
@@ -19,11 +19,11 @@ import scala.collection.immutable.ListMap
/** A default implementation of parameterizing the connectivity of the port where the tile is the master.
* Optional timing buffers and/or an optional CacheCork can be inserted in the interconnect's clock domain.
*/
case class ElementMasterPortParams(
case class HierarchicalElementMasterPortParams(
buffers: Int = 0,
cork: Option[Boolean] = None,
where: TLBusWrapperLocation = SBUS
) extends ElementPortParamsLike {
) extends HierarchicalElementPortParamsLike {
def injectNode(context: Attachable)(implicit p: Parameters): TLNode = {
(TLBuffer.chainNode(buffers) :=* cork.map { u => TLCacheCork(unsafe = u) } .getOrElse { TLTempNode() })
}
@@ -32,12 +32,12 @@ case class ElementMasterPortParams(
/** A default implementation of parameterizing the connectivity of the port giving access to slaves inside the tile.
* Optional timing buffers and/or an optional BusBlocker adapter can be inserted in the interconnect's clock domain.
*/
case class ElementSlavePortParams(
case class HierarchicalElementSlavePortParams(
buffers: Int = 0,
blockerCtrlAddr: Option[BigInt] = None,
blockerCtrlWhere: TLBusWrapperLocation = CBUS,
where: TLBusWrapperLocation = CBUS
) extends ElementPortParamsLike {
) extends HierarchicalElementPortParamsLike {
def injectNode(context: Attachable)(implicit p: Parameters): TLNode = {
val controlBus = context.locateTLBusWrapper(where)
val blockerBus = context.locateTLBusWrapper(blockerCtrlWhere)
@@ -51,10 +51,10 @@ case class ElementSlavePortParams(
}
}

/** InstantiatesTiles adds a Config-urable sequence of Elements of any type
/** InstantiatesTiles adds a Config-urable sequence of HierarchicalElements of any type
* to the subsystem class into which it is mixed.
*/
trait InstantiatesElements { this: LazyModule with Attachable =>
trait InstantiatesHierarchicalElements { this: LazyModule with Attachable =>
val location: HierarchicalLocation

/** Record the order in which to instantiate all tiles, based on statically-assigned ids.
@@ -78,7 +78,7 @@ trait InstantiatesElements { this: LazyModule with Attachable =>
case (instantiated, params) => instantiated + (params.clusterParams.clusterId -> params.instantiate(clusterParams, instantiated)(p))
}

val element_prci_domains: Seq[ElementPRCIDomain[_]] = tile_prci_domains.values.toSeq ++ cluster_prci_domains.values.toSeq
val element_prci_domains: Seq[HierarchicalElementPRCIDomain[_]] = tile_prci_domains.values.toSeq ++ cluster_prci_domains.values.toSeq

val leafTiles: ListMap[Int, BaseTile] = tile_prci_domains.mapValues(_.element.asInstanceOf[BaseTile]).to(ListMap)
val totalTiles: ListMap[Int, BaseTile] = (leafTiles ++ cluster_prci_domains.values.map(_.element.totalTiles).flatten)
@@ -94,8 +94,8 @@ trait InstantiatesElements { this: LazyModule with Attachable =>
}

/** HasTiles instantiates and also connects a Config-urable sequence of tiles of any type to subsystem interconnect resources. */
trait HasElements extends DefaultElementContextType
{ this: LazyModule with Attachable with InstantiatesElements =>
trait HasHierarchicalElements extends DefaultHierarchicalElementContextType
{ this: LazyModule with Attachable with InstantiatesHierarchicalElements =>
implicit val p: Parameters

// connect all the tiles to interconnect attachment points made available in this subsystem context
@@ -110,8 +110,8 @@ trait HasElements extends DefaultElementContextType
/** Provides some Chisel connectivity to certain tile IOs
* This trait is intended for the root subsystem
*/
trait HasElementsRootContextModuleImp extends LazyRawModuleImp {
val outer: InstantiatesElements with HasElements with HasElementsRootContext with HasTileInputConstants
trait HasHierarchicalElementsRootContextModuleImp extends LazyRawModuleImp {
val outer: InstantiatesHierarchicalElements with HasHierarchicalElements with HasHierarchicalElementsRootContext with HasTileInputConstants

val reset_vector = outer.tileResetVectorIONodes.zipWithIndex.map { case (n, i) => n.makeIO(s"reset_vector_$i") }
val tile_hartids = outer.tileHartIdIONodes.zipWithIndex.map { case (n, i) => n.makeIO(s"tile_hartids_$i") }
@@ -138,7 +138,7 @@ trait HasElementsRootContextModuleImp extends LazyRawModuleImp {
* BaseTiles subtypes with different needs can extend this trait to provide themselves with
* additional external connection points.
*/
trait DefaultElementContextType
trait DefaultHierarchicalElementContextType
extends Attachable
with HasTileNotificationSinks
{ this: LazyModule with Attachable =>
@@ -155,10 +155,10 @@ trait DefaultElementContextType
}

/** This trait provides the tile attachment context for the root (outermost) subsystem */
trait HasElementsRootContext
{ this: HasElements
trait HasHierarchicalElementsRootContext
{ this: HasHierarchicalElements
with HasTileNotificationSinks
with InstantiatesElements =>
with InstantiatesHierarchicalElements =>

val clintOpt: Option[CLINT]
val plicOpt: Option[TLPLIC]
6 changes: 3 additions & 3 deletions src/main/scala/subsystem/HasTiles.scala
Original file line number Diff line number Diff line change
@@ -51,7 +51,7 @@ case object HasTilesExternalResetVectorKey extends Field[Boolean](true)
* they may be either tied to a contant value or programmed during boot or reset.
* They need to be instantiated before tiles are attached within the subsystem containing them.
*/
trait HasTileInputConstants { this: LazyModule with Attachable with InstantiatesElements =>
trait HasTileInputConstants { this: LazyModule with Attachable with InstantiatesHierarchicalElements =>
/** tileHartIdNode is used to collect publishers and subscribers of hartids. */
val tileHartIdNodes: ListMap[Int, BundleBridgeEphemeralNode[UInt]] = (0 until nTotalTiles).map { i =>
(i, BundleBridgeEphemeralNode[UInt]())
@@ -150,9 +150,9 @@ trait HasTileNotificationSinks { this: LazyModule =>
*/
trait CanAttachTile {
type TileType <: BaseTile
type TileContextType <: DefaultElementContextType
type TileContextType <: DefaultHierarchicalElementContextType
def tileParams: InstantiableTileParams[TileType]
def crossingParams: ElementCrossingParamsLike
def crossingParams: HierarchicalElementCrossingParamsLike

/** Narrow waist through which all tiles are intended to pass while being instantiated. */
def instantiate(allTileParams: Seq[TileParams], instantiatedTiles: ListMap[Int, TilePRCIDomain[_]])(implicit p: Parameters): TilePRCIDomain[TileType] = {
Original file line number Diff line number Diff line change
@@ -14,22 +14,22 @@ import freechips.rocketchip.util._
import freechips.rocketchip.devices.debug.{TLDebugModule}
import freechips.rocketchip.devices.tilelink._

trait ElementParams {
trait HierarchicalElementParams {
val baseName: String // duplicated instances shouuld share a base name
val uniqueName: String
val clockSinkParams: ClockSinkParameters
}

abstract class InstantiableElementParams[ElementType <: BaseElement] extends ElementParams
abstract class InstantiableHierarchicalElementParams[ElementType <: BaseHierarchicalElement] extends HierarchicalElementParams

/** An interface for describing the parameteization of how Elements are connected to interconnects */
trait ElementCrossingParamsLike {
/** An interface for describing the parameteization of how HierarchicalElements are connected to interconnects */
trait HierarchicalElementCrossingParamsLike {
/** The type of clock crossing that should be inserted at the element boundary. */
def crossingType: ClockCrossingType
/** Parameters describing the contents and behavior of the point where the element is attached as an interconnect master. */
def master: ElementPortParamsLike
def master: HierarchicalElementPortParamsLike
/** Parameters describing the contents and behavior of the point where the element is attached as an interconnect slave. */
def slave: ElementPortParamsLike
def slave: HierarchicalElementPortParamsLike
/** The subnetwork location of the device selecting the apparent base address of MMIO devices inside the element */
def mmioBaseAddressPrefixWhere: TLBusWrapperLocation
/** Inject a reset management subgraph that effects the element child reset only */
@@ -39,18 +39,18 @@ trait ElementCrossingParamsLike {
}

/** An interface for describing the parameterization of how a particular element port is connected to an interconnect */
trait ElementPortParamsLike {
trait HierarchicalElementPortParamsLike {
/** The subnetwork location of the interconnect to which this element port should be connected. */
def where: TLBusWrapperLocation
/** Allows port-specific adapters to be injected into the interconnect side of the attachment point. */
def injectNode(context: Attachable)(implicit p: Parameters): TLNode
}

abstract class BaseElement (val crossing: ClockCrossingType)(implicit p: Parameters)
abstract class BaseHierarchicalElement (val crossing: ClockCrossingType)(implicit p: Parameters)
extends LazyModule()(p)
with CrossesToOnlyOneClockDomain
{
def module: BaseElementModuleImp[BaseElement]
def module: BaseHierarchicalElementModuleImp[BaseHierarchicalElement]

protected val tlOtherMastersNode = TLIdentityNode()
protected val tlMasterXbar = LazyModule(new TLXbar)
@@ -79,5 +79,5 @@ abstract class BaseElement (val crossing: ClockCrossingType)(implicit p: Paramet

}

abstract class BaseElementModuleImp[+L <: BaseElement](val outer: L) extends LazyModuleImp(outer)
abstract class BaseHierarchicalElementModuleImp[+L <: BaseHierarchicalElement](val outer: L) extends LazyModuleImp(outer)

Original file line number Diff line number Diff line change
@@ -19,7 +19,7 @@ import freechips.rocketchip.util.{TraceCoreInterface}
*
* This does not add a layer of the module hierarchy.
*/
class ElementResetDomain(clockSinkParams: ClockSinkParameters, resetCrossingType: ResetCrossingType)
class HierarchicalElementResetDomain(clockSinkParams: ClockSinkParameters, resetCrossingType: ResetCrossingType)
(implicit p: Parameters)
extends ResetDomain
with CrossesToOnlyOneResetDomain
@@ -38,14 +38,14 @@ class ElementResetDomain(clockSinkParams: ClockSinkParameters, resetCrossingType
* hierarchical P&R boundary buffers, core-local interrupt handling,
* and any other IOs related to PRCI control.
*/
abstract class ElementPRCIDomain[T <: BaseElement](
abstract class HierarchicalElementPRCIDomain[T <: BaseHierarchicalElement](
clockSinkParams: ClockSinkParameters,
crossingParams: ElementCrossingParamsLike)
crossingParams: HierarchicalElementCrossingParamsLike)
(implicit p: Parameters)
extends ClockDomain
{
val element: T
val element_reset_domain = LazyModule(new ElementResetDomain(clockSinkParams, crossingParams.resetCrossingType))
val element_reset_domain = LazyModule(new HierarchicalElementResetDomain(clockSinkParams, crossingParams.resetCrossingType))
val tapClockNode = ClockIdentityNode()
val clockNode = FixedClockBroadcast() :=* tapClockNode
lazy val clockBundle = tapClockNode.in.head._1
16 changes: 8 additions & 8 deletions src/main/scala/subsystem/RocketSubsystem.scala
Original file line number Diff line number Diff line change
@@ -12,20 +12,20 @@ import freechips.rocketchip.devices.tilelink.{CanHavePeripheryCLINT, CanHavePeri

case class RocketCrossingParams(
crossingType: ClockCrossingType = SynchronousCrossing(),
master: ElementPortParamsLike = ElementMasterPortParams(),
slave: ElementSlavePortParams = ElementSlavePortParams(),
master: HierarchicalElementPortParamsLike = HierarchicalElementMasterPortParams(),
slave: HierarchicalElementSlavePortParams = HierarchicalElementSlavePortParams(),
mmioBaseAddressPrefixWhere: TLBusWrapperLocation = CBUS,
resetCrossingType: ResetCrossingType = NoResetCrossing(),
forceSeparateClockReset: Boolean = false
) extends ElementCrossingParamsLike
) extends HierarchicalElementCrossingParamsLike

case class RocketTileAttachParams(
tileParams: RocketTileParams,
crossingParams: RocketCrossingParams
) extends CanAttachTile { type TileType = RocketTile }

trait HasRocketTiles {
this: BaseSubsystem with InstantiatesElements =>
this: BaseSubsystem with InstantiatesHierarchicalElements =>
val rocketTiles = totalTiles.values.collect { case r: RocketTile => r }

def coreMonitorBundles = (rocketTiles map { t =>
@@ -34,20 +34,20 @@ trait HasRocketTiles {
}

class RocketSubsystem(implicit p: Parameters) extends BaseSubsystem
with InstantiatesElements
with InstantiatesHierarchicalElements
with HasTileNotificationSinks
with HasTileInputConstants
with CanHavePeripheryCLINT
with CanHavePeripheryPLIC
with HasPeripheryDebug
with HasElementsRootContext
with HasElements
with HasHierarchicalElementsRootContext
with HasHierarchicalElements
with HasCoreMonitorBundles
with HasRocketTiles
{
override lazy val module = new RocketSubsystemModuleImp(this)
}

class RocketSubsystemModuleImp[+L <: RocketSubsystem](_outer: L) extends BaseSubsystemModuleImp(_outer)
with HasElementsRootContextModuleImp
with HasHierarchicalElementsRootContextModuleImp

10 changes: 5 additions & 5 deletions src/main/scala/tile/BaseTile.scala
Original file line number Diff line number Diff line change
@@ -18,7 +18,7 @@ case object TileVisibilityNodeKey extends Field[TLEphemeralNode]
case object TileKey extends Field[TileParams]
case object LookupByHartId extends Field[LookupByHartIdImpl]

trait TileParams extends ElementParams {
trait TileParams extends HierarchicalElementParams {
val core: CoreParams
val icache: Option[ICacheParams]
val dcache: Option[DCacheParams]
@@ -28,9 +28,9 @@ trait TileParams extends ElementParams {
}

abstract class InstantiableTileParams[TileType <: BaseTile]
extends InstantiableElementParams[TileType]
extends InstantiableHierarchicalElementParams[TileType]
with TileParams {
def instantiate(crossing: ElementCrossingParamsLike, lookup: LookupByHartIdImpl)
def instantiate(crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)
(implicit p: Parameters): TileType
}

@@ -188,7 +188,7 @@ trait HasTileParameters extends HasNonDiplomaticTileParameters {

/** Base class for all Tiles that use TileLink */
abstract class BaseTile private (crossing: ClockCrossingType, q: Parameters)
extends BaseElement(crossing)(q)
extends BaseHierarchicalElement(crossing)(q)
with HasNonDiplomaticTileParameters
{
// Public constructor alters Parameters to supply some legacy compatibility keys
@@ -347,4 +347,4 @@ abstract class BaseTile private (crossing: ClockCrossingType, q: Parameters)
this.suggestName(tileParams.baseName)
}

abstract class BaseTileModuleImp[+L <: BaseTile](outer: L) extends BaseElementModuleImp[L](outer)
abstract class BaseTileModuleImp[+L <: BaseTile](outer: L) extends BaseHierarchicalElementModuleImp[L](outer)
6 changes: 3 additions & 3 deletions src/main/scala/tile/RocketTile.scala
Original file line number Diff line number Diff line change
@@ -10,7 +10,7 @@ import freechips.rocketchip.diplomacy._
import freechips.rocketchip.interrupts._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.rocket._
import freechips.rocketchip.subsystem.ElementCrossingParamsLike
import freechips.rocketchip.subsystem.HierarchicalElementCrossingParamsLike
import freechips.rocketchip.util._
import freechips.rocketchip.prci.{ClockSinkParameters}

@@ -32,7 +32,7 @@ case class RocketTileParams(
require(dcache.isDefined)
val baseName = "rockettile"
val uniqueName = s"${baseName}_$tileId"
def instantiate(crossing: ElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): RocketTile = {
def instantiate(crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): RocketTile = {
new RocketTile(this, crossing, lookup)
}
}
@@ -50,7 +50,7 @@ class RocketTile private(
with HasICacheFrontend
{
// Private constructor ensures altered LazyModule.p is used implicitly
def this(params: RocketTileParams, crossing: ElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters) =
def this(params: RocketTileParams, crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters) =
this(params, crossing.crossingType, lookup, p)

val intOutwardNode = rocketParams.beuAddr map { _ => IntIdentityNode() }
4 changes: 2 additions & 2 deletions src/main/scala/tile/TilePRCIDomain.scala
Original file line number Diff line number Diff line change
@@ -23,8 +23,8 @@ import freechips.rocketchip.util.{TraceCoreInterface}
*/
abstract class TilePRCIDomain[T <: BaseTile](
clockSinkParams: ClockSinkParameters,
crossingParams: ElementCrossingParamsLike)
crossingParams: HierarchicalElementCrossingParamsLike)
(implicit p: Parameters)
extends ElementPRCIDomain[T](clockSinkParams, crossingParams)
extends HierarchicalElementPRCIDomain[T](clockSinkParams, crossingParams)
{
}

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