vsd_openlane_workshop

This workshop is based on how to RTL netlist into a tape-out. This workshop is organized by VLSI system design in collaboration with NASSCOM.

Section 1 - Inception of open-source EDA, OpenLANE and Sky130 PDK

`Move to the directory where Openlane is Installed

cd Desktop/work/tools/openlane_working_dir/openlane

Start the Docker container and enter the OpenLANE shell:

docker

./flow.tcl -interactive`

Initilize the environment

package require openlane 0.9

The picorv32a Directory

prep -design picorv32a

Now we can see that there is a directory created(check timestamp) under which we could navigate to the runs directory where we can find the merged.lef

We can see the specs about the vias metal layer cuts and the dimension

Synthesis

run_synthesis

After Running the synthesis command we can see the update inside the design directory of openlane where we have the picorv32a (check the modified date) /Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/12-05_11/results/synthesis

Synthesis results

Flop ratio = (Number of D flip flops)/(Total number of cells)

       = 1613/14876
       
       = 0.1084

DFF's percent = Flop ratio * 100 = 10.84%

Section 2 - Goodfloorplan vs bad floorplan and introduction to library cells

What's inside the README.md of Config files?

This gives a documentation the various settings are user can use by help of the switches we we can set in the ~/Desktop/work/tools/openlane_working_dir/openlane/configuration/floorplan.tcl

Inside the floorplan.tcl

In the openlane interactive mode

run_floorplan

floorplan.def was updated as shown in the below image

Reviewing the floorplan reports

~/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/16-05_05-22/results/floorplan

picorv32a.floorplan.def.png

Inside the picorv32a.floorplan.def

OBSERVATIONS FROM THE FLOORPLAN RESULTS

Given 1000 unit distance = 1 Micron

Die width = 660685 in unit distance = 660.685 microns

Die height = 671405 in unit distance = 671.405 microns

Area of the die = 660.685*671.405 = 443587.212425 sq microns.

Layout in Magic Tool

Inside the config.tcl

~/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/config.tcl

We need a lef and def file along with pdk's techfile into order to map accordingly and view the floorplan in the Magic

magic -T /home/vsduser/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read picorv32a.floorplan.def &

Decap cells

An overview of decap tap cells

Click on any cell and select it, Then press "S" which will open a tkcon window and type "what" to get a brief note on the selected cell"

Standard cells placed at the bottom of the layout

Complete layout

Right click on z to zoom

PLACEMENT

run_placement

PLACEMENT RESULTS

Change directory to path containing generated placement def

cd Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/17-03_12-06/results/placement/

Command to load the placement def in magic tool

magic -T /home/vsduser/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read picorv32a.placement.def &

Screenshot of floorplan def in magic

TRYING DIFFERENT SWITCHES

With the default configuration

In the openlane interavtive window

set ::env(FP_IO_MODE) 2

inside the ~/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/16-05_05-22/results/floorplan

magic -T /home/vsduser/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read picorv32a.floorplan.def &

Section 3 - Design library cell using Magic Layout and ngspice characterization

git clone https://github.com/nickson-jose/vsdstdcelldesign.git

We need to clone the working directory in the above github repo

To view th CMOS inverter layout use

magic -T sky130A.tech sky130_inv.mag &

DEFINING THE LAYERS

Extracting the SPICE netlist

Commands for spice extraction of the custom inverter layout to be used in tkcon window of magic

`# Check current directory pwd

Extraction command to extract to .ext format extract all

Before converting ext to spice this command enable the parasitic extraction also ext2spice cthresh 0 rthresh 0

Converting to ext to spice ext2spice

Inside the sky130_inv.ext We can witness the extracted netlist information

Actual extracted spice netlist

Modified extracted spice netlist

`.option scale=0.01u

.include ./libs/pshort.lib

.include ./libs/nshort.lib

//.subckt sky130_inv A Y VPWR VGND

M1001 Y A VGND VGND nshort_model.0 ad=1.44n pd=0.152m as=1.37n ps=0.148m w=35 l=23

M1000 Y A VPWR VPWR pshort_model.0 ad=1.44n pd=0.152m as=1.52n ps=0.156m w=37 l=23

VDD VPWR 0 3.3V

VSS VGND 0 0V

C6 Y 0 2fF

Va A VGND PULSE(0V 3.3V 0 0.1ns 0.1ns 2ns 4ns)

C0 A VPWR 0.0774fF

C1 Y VPWR 0.117fF

C2 A Y 0.07f4fF

C3 Y VGND 0.279fF

C4 A VGND 0.45f

C5 VPWR VGND 0.781f

//.ends

.tran 1n 20n

.control

run

.endc

.end`

SPICE SIMULATION RESULTS

RISE TIME

x0 = 2.16151e-09, y0 = 0.659639 x0 = 2.20386e-09, y0 = 2.63012

Rise time transition 20% to 80% - time value = 43ps

FALL TIME

x0 = 4.04043e-09, y0 = 0.264059 x0 = 4.06827e-09, y0 = 0.662766

Fall time transition 20% to 80% - time value = 28ps

CELL RISE DELAY Calculated at 50% of VDD = 35ps

    x0 = 2.15e-09, y0 = 1.65189  x0 = 2.185e-09, y0 = 1.65094

CELL FALL DELAY Calculated at 50% of VDD = 20ps

    x0 = 4.06051e-09, y0 = 1.65147  x0 = 4.05492e-09, y0 = 1.65

DRC ERRORS AND TECH FILE - AN OVERVIEW

Link to Sky130 Periphery rules: https://skywater-pdk.readthedocs.io/en/main/rules/periphery.html

Commands to download and view the corrupted skywater process magic tech file and associated files to perform drc corrections

Change to home directory cd

Command to download the lab files wget http://opencircuitdesign.com/open_pdks/archive/drc_tests.tgz

Since lab file is compressed command to extract it tar xfz drc_tests.tgz

Change directory into the lab folder cd drc_tests

List all files and directories present in the current directory ls -al

Command to view .magicrc file gvim .magicrc

Command to open magic tool in better graphics magic -d XR &

Scrrenshots of commands run

Screenshot of .magicrc file

open met3.mag in magic

Fixing poly.9 error in Sky 130 tech-file

open the plu.mag file

gvim sky130A.tech

change to allpolynonres

implement poly resistor spacing to diffusion and tap

add this line--------------------- spacing xhrpoly,uhrpoly,xpc allpolynonres 480 touching illegal
"xhrpoly/uhrpoly resistor spacing to diffusion < %d (poly.9)"

Describing DRC error as Geometrical Construct

First we need to open nwell.mag

New commands inserted in sky130A.tech file to update drc

Commands to run in tkcon window

Loading updated tech file tech load sky130A.tech

Change drc style to drc full drc style drc(full)

Must re-run drc check to see updated drc errors drc check

Selecting region displaying the new errors and getting the error messages drc why

After implementing the rules mentioned above

Section 4 - Pre-layout timing analysis and importance of good clock tree

Change directory to vsdstdcelldesign

cd Desktop/work/tools/openlane_working_dir/openlane/vsdstdcelldesign

Command to open custom inverter layout in magic

magic -T sky130A.tech sky130_inv.mag &

Get syntax for grid command

help grid

Set grid values accordingly

grid 0.46um 0.34um 0.23um 0.17um

Checking the conditons

Horizontal track pitch = 0.46 um

Width of standard cell = 1.38 um = 0.46*3

Height of the standard cell = 2.72 um = 0.34*8

Next step is to save the finalized layout with custom name and open it

Command to save as

save sky130_vsdinv.mag

Command to open custom inverter layout in magic

magic -T sky130A.tech sky130_vsdinv.mag &

Screenshot of newly created lef file

Now the newly generated lef and associated required lib files to 'picorv32a' design 'src' directory

To Copy files to picorv32a design src directory

Copy lef file

cp sky130_vsdinv.lef ~/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/src/

List and check whether it's copied

ls ~/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/src/

Copy lib files

cp libs/sky130_fd_sc_hd__* ~/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/src/

List and check whether it's copied

ls ~/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/src/

Edit config.tcl

Running Openlane flow synthesis with newly inserted custom inverter cell

After running the commands

After running the synthesis we got,

Chip area for module '\picorv32a' : 147712.918400

tns -711.59

wns -23.89

Commands to view and change parameters to improve timing and run synthesis

Now once again we have to prep design so as to update variables

prep -design picorv32a -tag 29-05_12-20 -overwrite

Addiitional commands to include newly added lef to openlane flow merged.lef

set lefs [glob $::env(DESIGN_DIR)/src/*.lef]

add_lefs -src $lefs

Command to display current value of variable SYNTH_STRATEGY

echo $::env(SYNTH_STRATEGY)

Command to set new value for SYNTH_STRATEGY

set ::env(SYNTH_STRATEGY) "DELAY 3"

Command to display current value of variable SYNTH_BUFFERING to check whether it's enabled

echo $::env(SYNTH_BUFFERING)

Command to display current value of variable SYNTH_SIZING

echo $::env(SYNTH_SIZING)

Command to set new value for SYNTH_SIZING

set ::env(SYNTH_SIZING) 1

Command to display current value of variable SYNTH_DRIVING_CELL to check whether it's the proper cell or not

echo $::env(SYNTH_DRIVING_CELL)

Now that the design is prepped and ready, we can run synthesis using following command

run_synthesis

merged.lef in tmp directoy

After running the above commands

Now run the floorplan

As we are facing issues in run_floorplan command , we will use the below mentioned commands

Follwing commands are alltogather sourced in "run_floorplan" command

init_floorplan

place_io

tap_decap_or

Now run_placement

Commands to load placement def in magic in another terminal

Change directory to path containing generated placement def

cd Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/29-05_12-20/results/placement/

Command to load the placement def in magic tool

magic -T /home/vsduser/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read picorv32a.placement.def &

Screenshot of the customer inverter interested in placemnt def with proper abutment

Command to view internal connectivity layers

expand