This repo contains some Migen modules created to support some MiSoC features on the Xilinx Zynq SoC. A Zedboard is used for testing, the existing platform from Migen is used as baseline and extended as necessary.
- wrapper for PS7
- AXI2CSR
- P2P interconnect
- InterconnectShared
- Crossbar
- Writer, AXI3 Slave + CoreLink DMA-330 DMA Controller Peripheral Request Interface (PRI)
By now only P2P interconnect is in actual use, where M_AXI_GP0 is wired to a
custom AXI3 slave and M_AXI_GP1 is wired to a AXI2CSR bridge.
- Device-tree overlay generator for iomem, irqs, firmware
-
bitstream-fixto convert .bit file to a fpga-mgr compatible .bin
Device-tree overlay is supported by Linux, currently .dts is crafted manually
but shall be automatically generated.
Overlays with firmware loading has been tested on a 4.9 Linux.
To allow for phandles DTS_FLAGS+='-@ -H epapr' may be used.
Released under the MIT license, see LICENSE file for info.
