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BX synchronization #64

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merged 3 commits into from
Oct 28, 2024
Merged

BX synchronization #64

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efa78e0
Added changes to propagate TP_bx_vld to tf_merge_stream and output bx…
mcoshiro Oct 10, 2024
20898b2
Cleanup comment
mcoshiro Oct 10, 2024
dbd9e73
Incorporate Andrew's suggestion; make TPAR memories into URAM
mcoshiro Oct 23, 2024
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20 changes: 16 additions & 4 deletions WriteVHDLSyntax.py
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Original file line number Diff line number Diff line change
Expand Up @@ -420,6 +420,8 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl

interface = int(memInfo.is_final) - int(memInfo.is_initial)

first_merge_streamer = True

for memmod in memList:

nmem = 0
Expand Down Expand Up @@ -592,6 +594,8 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl
parameterlist += " NUM_PHI_BINS => 8,\n"
parameterlist += " NUM_RZ_BINS => 16,\n"
parameterlist += " NUM_COPY => "+str(ncopy)+"\n"
if "TPAR" in mem:
parameterlist += " MEM_TYPE => \"ultra\",\n"

#FIXME implement delay for disks
# Write ports
Expand Down Expand Up @@ -646,10 +650,16 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl
merge_parameterlist += " NUM_INPUTS => "+str(numInputs)+",\n"
merge_parameterlist += " NUM_EXTRA_BITS => 2,\n"
merge_portlist += " bx_in => TP_bx_out,\n"
merge_portlist += " bx_in_vld => TP_bx_out_vld,\n"
merge_portlist += " rst => '0',\n"
merge_portlist += " clk => clk,\n"
merge_portlist += " enb_arr => open,\n"
merge_portlist += " bx_out => open,\n"
#This will make output for first stream_merge module (is there a less hacky way?)
if first_merge_streamer:
merge_portlist += " bx_out => TP_bx_out_merged,\n"
first_merge_streamer = False
else:
merge_portlist += " bx_out => open,\n"
merge_portlist += " merged_dout => MPAR_"+seed+PCGroup+"_stream_V_dout,\n"
for i in range(4): merge_portlist += " din"+str(i)+"=>TPAR_"+seed+PCGroup[i%numInputs]+"_V_dout,\n"
for i in range(4): merge_portlist += " nent"+str(i)+"=>TPAR_"+seed+PCGroup[i%numInputs]+"_AV_dout_nent,\n"
Expand All @@ -668,6 +678,7 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl
merge_parameterlist += " NUM_INPUTS => "+str(numInputs)+",\n"
merge_parameterlist += " NUM_EXTRA_BITS => 0,\n"
merge_portlist += " bx_in => TP_bx_out,\n"
merge_portlist += " bx_in_vld => TP_bx_out_vld,\n"
merge_portlist += " rst => '0',\n"
merge_portlist += " clk => clk,\n"
merge_portlist += " enb_arr => open,\n"
Expand Down Expand Up @@ -782,6 +793,8 @@ def writeControlSignals_interface(initial_proc, final_procs, notfinal_procs, del
string_ctrl_signals += " reset : in std_logic;\n"
string_ctrl_signals += " "+initial_proc+"_start : in std_logic;\n"
string_ctrl_signals += " "+initial_proc+"_bx_in : in std_logic_vector(2 downto 0);\n"
if split == 1:
string_ctrl_signals += " TP_bx_out_merged : out std_logic_vector(2 downto 0);\n"
if split == 2:
string_ctrl_signals += " "+initial_proc+"_bx_out : out std_logic_vector(2 downto 0);\n"
string_ctrl_signals += " "+initial_proc+"_bx_out_vld : out std_logic;\n"
Expand Down Expand Up @@ -1527,8 +1540,7 @@ def writeStartSwitchAndInternalBX(module,mem,extraports=False, delay = 0, first_
int_ctrl_func += " bx => PC_bx_out,\n"
int_ctrl_func += " start => PC_done\n"
int_ctrl_func += " );\n\n"



if first_proc:
mtype_up = module.mtype_short()
else:
Expand Down Expand Up @@ -1613,7 +1625,7 @@ def writeProcBXPort(modName,isInput,isInitial,first_of_type,delay):
if first_of_type and not ("VMSMER" in modName or "PC" in modName):
bx_str += " bx_o_V => "+modName.split("_")[0]+"_bx_out,\n"
#bx_str += " bx_o_V_ap_vld => "+modName+"_bx_out_vld,\n"
if "FT_" in modName:
if ("FT_" in modName) or ("TP_" in modName):
bx_str += " bx_o_V_ap_vld => "+modName.split("_")[0]+"_bx_out_vld,\n"
else:
bx_str += " bx_o_V_ap_vld => open,\n"
Expand Down
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