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.buildinfo

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+# Sphinx build info version 1
+# This file hashes the configuration used when building these files. When it is not found, a full rebuild will be done.
+config: 94411eb37a8805e2ec2f91980fdea775
+tags: 645f666f9bcd5a90fca523b33c5a78b7

_sources/exercise.md.txt

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+# Exercise
+
+## Objective
+- To try out the `make` command on different makefiles.
+
+## Steps
+In this exercise we will execute `make` on different makefiles.
+You will also edit an Makefile and try to create your own Makefile.
+
+### Example 1
+- **Step 1**: Logon on to a Linux system like Dardel
+- **Step 2**: Go to [makefile-examples](https://github.com/coderefinery/makefile-examples) repository
+and clone the repository to your user space on the Linux system.
+- **Step 3**: Change to the subdirectory `make-examples`, list the files. You will see that there is
+4 makefile examples in the repository:
+```sh
+git clone https://github.com/coderefinery/makefile-examples.git
+cd makefile-examples
+ls
+```
+- **Step 4**: Change to subdirectory `example_1`. Take a look at the `makefile` and execute make. You will see that `make` executes
+the command to build the executable. Test the executable and then remove it.
+```sh
+cd example_1
+cat Makefile
+make
+./hello.exe
+rm hello.exe
+```
+- **Step 5**: Introduce an error in the `example_1` makefile. Open the `Makefile` in an editor and
+replace the tab in front of the command for the target with spaces. Save the file and execute
+`make` again. This time you get an error:`Makefile:2: *** missing separator.  Stop.`
+
+### Example 2
+- **Step 1**: Change directory to `example_2`. Take a look at the `Makefile` and execute `make`.
+See how different object files are created in the subdirectory.
+```sh
+# from subdirectory example_1
+cd ../example_2
+ls
+cat Makefile
+make
+ls
+```
+
+- **Step 2**: Remove a object file and rerun `make`. Observe how `make` only build the missing
+object file and the rebuilds the executable since it is dependent on the newly built object file.
+```sh
+rm module.o
+make
+```
+
+- **Step 3**: Remove the executable and rerun `make`. Observe that only the step to build the
+executable is taken. The object files that the executable is dependent on is untouched.
+```sh
+rm hello.exe
+make
+```
+
+### Example 3
+Here you will try to create a makefile. Change into the subdirectory and observe that you have
+source files in the subdirectory `src`. How will you start out? The `Makefile` in example 2
+build an executable from source files in a `src` subdirectory. Let us see if we can use it as a
+starting point.
+
+- **Step 1**: Copy the `Makefile` from example 2 and execute make. You see that you get an error message
+from make: `make: *** No rule to make target `hello.o', needed by `hello.exe'.  Stop.`
+- **Step 2**: Open an editor (nano, vim) and replace references to `hello.exe` in the `Makefile`
+with `calculation.exe`, both as a target as a dependency. Execute `make` again and observe the
+erro message: `src/calculation.c:4:10: fatal error: 'example_math.h' file not found`
+This is an error message from the compilation of `calculation.c`. The compiler cannot find
+the include file `example_math.h` which resides in the subdirectory `include`.
+- **Step 3**: To find the include file, the compile needs to be told to look in the `include` subdirectory.
+We do this by adding the CFLAGS=-I include to the `Makefile`. Add it at the top of the `Makefile`, after
+the .PHONY statement, like this:
+```makefile
+.PHONY: clean all install
+CFLAGS=-I include
+```
+
+- **Step 4**: Rerun `make` and observe how the build of `calculation.c` completes, but the build
+of the executable fails due to missing of `module.o`:
+`make: *** No rule to make target module.o, needed by calculation.exe.  Stop.`
+```sh
+make
+```
+
+- **Step 5**: Edit the `makefile` again and replace `module.o` with `sin.o cos.o` as
+dependencies for `calculatione.exe`.
+```makefile
+# The calculation.exe target in the Makefile
+calculation.exe: calculation.o sin.o cos.o
+	$(CC) $(CFLAGS) $^ -o $@
+```
+```sh
+make
+ls
+./calculation.exe
+make clean
+make
+```
+
+### Example 4
+In this example the builds, the object files and the executable, ends up in its own subdirectory `bin`.
+This separates the source files and the top `Makefile` from the binaries. This is very tidy and useful.
+Take a look at the make file, see how a function creates the necessary subdirectory, and how binaries
+are placed in an own subdirectory:
+```sh
+cd ../example_4
+ls
+cat Makefile
+make
+touch src/cos.c  # simulate a update of src/cos.c
+make
+make clean
+ls
+```

_sources/index.rst.txt

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+.. Example documentation master file, created by
+   sphinx-quickstart on Sat Sep 23 20:35:12 2023.
+   You can adapt this file completely to your liking, but it should at least
+   contain the root `toctree` directive.
+
+Welcome to a lesson about `make`!
+===================================
+
+.. toctree::
+   :maxdepth: 2
+   :caption: Contents:
+
+   motivation.md
+   rules.md
+   exercise.md
+   resources.md

_sources/motivation.md.txt

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+# Motivation 
+The `make` program is intended to automate the mundane aspects of transforming source code into an executable. 
+The advantages of `make` over scripts is that you can specify relationships between the elements of your program
+to `make`. With the knowledge of the relationships and timestamps it figures out the necessary steps to be
+redone to produce the desired program each time.
+
+## A simple Makefile
+The specification that `make` uses is saved in a file named _makefile_. Here is a _makefile_ to build the
+traditional "Hello, World" program.
+
+```makefile
+hello: hello.c
+    gcc hello.c -o hello
+```
+
+To build the program we execute `make` by typing:
+```shell
+$ make
+```
+This will cause the `make` program to read the _makefile_ and build the first target it finds there.
+
+## Targets and Prerequisites
+A _makefile_ contains a set of rules to build an application. The first rule seen by `make` is used as the
+_default rule_. A _rule_ consists of three parts: the target, its prerequisites, and the command(s) to peform:
+
+```makefile
+target1: prerequisite1 prerequisite2
+    command1
+    command2
+
+target2(=prerequisite1): prerequisite3 prerequisite4 prerequisite5
+    command3
+
+target3(=prerequisite2): prerequisite6 prerequisite7
+    command4
+
+target4(=prerequisite3): prerequisite8 prerequisite9
+    command5
+
+target5(=prerequisite4): prerequisite10 prerequisite11
+    command6
+```
+
+The _target_ is the file that must be made. The _prerequisites_ or _dependents_ are those files that must
+exist before the target can be successfully created. And _commands_ are those shell commands that will
+create the target from the prerequisites.
+
+## A Dependecy Graph
+![A Dependency Graph](img/dependency_graph.001.jpeg)
+When `make` evaluates a rule, it begins by finding the files indicated by the prerequisites and target. 
+If any of the prerequisites has an associated rule, `make` attempts to update those first. Next, the target
+file is considered. If any prerequisite is newer than the target, the target is remade by executing the
+commands. If  any of the commands generates an error, the building of the target is terminated and `make`
+exits.
+
+The previous example assume that:
+- All the project source code and the _makefile_ are stored in a single directory.
+- The `make` description file is called _makefile, Makefile or GNUMakefile_.
+- The _makefile_ resides in the user's current directory when executing the `make` command.
+

_sources/resources.md.txt

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+# Resources
+
+- [The GNU Make documentation page](https://www.gnu.org/software/make/manual/)
+- [Managing Projects with GNU Make, Third Edition](https://www.oreilly.com/openbook/make3/book/index.csp)