devtools/td-layout-config: move payload image to physical memory

Maximum size of ROM space is 16MiB which limits the size of payload image that can be contained by image. Signed-off-by: Jiaqi Gao <[email protected]>
confidential-containers · Mar 31, 2024 · 8f0e276 · 8f0e276
1 parent ba13296
commit 8f0e276
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Showing 3 changed files with 42 additions and 48 deletions.
diff --git a/devtools/td-layout-config/config_memory_exec.json b/devtools/td-layout-config/config_memory_exec.json
@@ -10,6 +10,11 @@
             "size": "0x20000",
             "type": "Memory"
         },
+        {
+            "name": "ShimPayload",
+            "size": "0xC2D000",
+            "type": "Memory"
+        },
         {
             "name": "EventLog",
             "size": "0x100000",

diff --git a/devtools/td-layout-config/src/image.rs b/devtools/td-layout-config/src/image.rs
@@ -2,7 +2,7 @@ use serde::Deserialize;
 
 use super::{layout::LayoutConfig, render};
 
-const FIRMWARE_ROM_BASE: usize = 0xFF00_0000;
+const FIRMWARE_ROM_TOP: usize = 0xFFFF_FFFF;
 const FIRMWARE_ROM_SIZE: usize = 0x100_0000;
 
 #[derive(Deserialize, Debug, PartialEq)]
@@ -75,16 +75,14 @@ pub fn parse_image(data: String) -> String {
 
     // Build ROM layout at memory space: 0xFF00_0000 - 0xFFFF_FFFF
     // Payload image is not loaded into ROM space.
+    let rom_size = image_size - payload_size;
     let mut rom_layout =
-        LayoutConfig::new(FIRMWARE_ROM_BASE, FIRMWARE_ROM_BASE + FIRMWARE_ROM_SIZE);
+        LayoutConfig::new(FIRMWARE_ROM_TOP - rom_size + 1, FIRMWARE_ROM_TOP);
 
     if image_size > FIRMWARE_ROM_SIZE {
         panic!("Image size exceeds the maximum ROM space");
     }
 
-    if payload_size != 0 {
-        image_layout.reserve_low("Payload", payload_size, "Rom")
-    }
     rom_layout.reserve_low("Config", config_size, "Rom");
     rom_layout.reserve_low("Mailbox", mailbox_size, "Rom");
     rom_layout.reserve_low("TempStack", temp_stack_size, "Rom");

diff --git a/td-layout/src/build_time.rs b/td-layout/src/build_time.rs
@@ -17,62 +17,53 @@ Image Layout
 +----------------------------------------+ <- 0xC8E000
 |               TEMP_HEAP                |   (0x20000) 128 kB
 +----------------------------------------+ <- 0xCAE000
-|                  FREE                  |   (0x1000) 4 kB
-+----------------------------------------+ <- 0xCAF000
+|                  FREE                  |   (0x0) 0 B
++----------------------------------------+ <- 0xCAE000
 |                METADATA                |   (0x1000) 4 kB
-+----------------------------------------+ <- 0xCB0000
++----------------------------------------+ <- 0xCAF000
 |                  IPL                   |   (0x348000) 3.28 MB
-+----------------------------------------+ <- 0xFF8000
++----------------------------------------+ <- 0xFF7000
 |              RESET_VECTOR              |   (0x8000) 32 kB
-+----------------------------------------+ <- 0x1000000
-Image size: 0x1000000 (16 MB)
++----------------------------------------+ <- 0xFFF000
+Image size: 0xFFF000 (16.00 MB)
 */
 
-// Image Layout Configuration
-
+// Image configuration
+pub const TD_SHIM_IMAGE_SIZE: u32 = 0xFFF000;
 pub const TD_SHIM_PAYLOAD_OFFSET: u32 = 0x0;
-pub const TD_SHIM_PAYLOAD_SIZE: u32 = 0xC2D000; // 12.18 MB
-
 pub const TD_SHIM_CONFIG_OFFSET: u32 = 0xC2D000;
-pub const TD_SHIM_CONFIG_SIZE: u32 = 0x40000; // 256 kB
-
 pub const TD_SHIM_MAILBOX_OFFSET: u32 = 0xC6D000;
-pub const TD_SHIM_MAILBOX_SIZE: u32 = 0x1000; // 4 kB
-
 pub const TD_SHIM_TEMP_STACK_OFFSET: u32 = 0xC6E000;
-pub const TD_SHIM_TEMP_STACK_SIZE: u32 = 0x20000; // 128 kB
-
 pub const TD_SHIM_TEMP_HEAP_OFFSET: u32 = 0xC8E000;
-pub const TD_SHIM_TEMP_HEAP_SIZE: u32 = 0x20000; // 128 kB
-
 pub const TD_SHIM_FREE_OFFSET: u32 = 0xCAE000;
-pub const TD_SHIM_FREE_SIZE: u32 = 0x1000; // 4 kB
+pub const TD_SHIM_METADATA_OFFSET: u32 = 0xCAE000;
+pub const TD_SHIM_IPL_OFFSET: u32 = 0xCAF000;
+pub const TD_SHIM_RESET_VECTOR_OFFSET: u32 = 0xFF7000;
 
-pub const TD_SHIM_METADATA_OFFSET: u32 = 0xCAF000;
-pub const TD_SHIM_METADATA_SIZE: u32 = 0x1000; // 4 kB
+// Size of regions
+pub const TD_SHIM_PAYLOAD_SIZE: u32 = 0xC2D000;
+pub const TD_SHIM_CONFIG_SIZE: u32 = 0x40000;
+pub const TD_SHIM_MAILBOX_SIZE: u32 = 0x1000;
+pub const TD_SHIM_TEMP_STACK_SIZE: u32 = 0x20000;
+pub const TD_SHIM_TEMP_HEAP_SIZE: u32 = 0x20000;
+pub const TD_SHIM_FREE_SIZE: u32 = 0x0;
+pub const TD_SHIM_METADATA_SIZE: u32 = 0x1000;
+pub const TD_SHIM_IPL_SIZE: u32 = 0x348000;
+pub const TD_SHIM_RESET_VECTOR_SIZE: u32 = 0x8000;
 
-pub const TD_SHIM_IPL_OFFSET: u32 = 0xCB0000;
-pub const TD_SHIM_IPL_SIZE: u32 = 0x348000; // 3.28 MB
-
-pub const TD_SHIM_RESET_VECTOR_OFFSET: u32 = 0xFF8000;
-pub const TD_SHIM_RESET_VECTOR_SIZE: u32 = 0x8000; // 32 kB
-
-// Offset when Loading into Memory
-pub const TD_SHIM_FIRMWARE_BASE: u32 = 0xFF000000;
-pub const TD_SHIM_FIRMWARE_SIZE: u32 = 0x1000000;
+// ROM configuration
+pub const TD_SHIM_FIRMWARE_BASE: u32 = 0xFFC2E000;
+pub const TD_SHIM_FIRMWARE_SIZE: u32 = 0x3D1FFF;
+pub const TD_SHIM_CONFIG_BASE: u32 = 0xFFC2E000;
+pub const TD_SHIM_MAILBOX_BASE: u32 = 0xFFC6E000;
+pub const TD_SHIM_TEMP_STACK_BASE: u32 = 0xFFC6F000;
+pub const TD_SHIM_TEMP_HEAP_BASE: u32 = 0xFFC8F000;
+pub const TD_SHIM_FREE_BASE: u32 = 0xFFCAF000;
+pub const TD_SHIM_METADATA_BASE: u32 = 0xFFCAEFFF;
+pub const TD_SHIM_IPL_BASE: u32 = 0xFFCAFFFF;
+pub const TD_SHIM_RESET_VECTOR_BASE: u32 = 0xFFFF7FFF;
 
 // TD_SHIM_SEC_INFO_OFFSET equals to firmware size - metadata pointer offset -
 // OVMF GUID table size - SEC Core information size.
-pub const TD_SHIM_SEC_CORE_INFO_OFFSET: u32 = 0xFFFFAC;
-pub const TD_SHIM_SEC_CORE_INFO_BASE: u32 = 0xFFFFFFAC;
-
-// Base Address after Loaded into Memory
-pub const TD_SHIM_PAYLOAD_BASE: u32 = 0xFF000000;
-pub const TD_SHIM_CONFIG_BASE: u32 = 0xFFC2D000;
-pub const TD_SHIM_MAILBOX_BASE: u32 = 0xFFC6D000;
-pub const TD_SHIM_TEMP_STACK_BASE: u32 = 0xFFC6E000;
-pub const TD_SHIM_TEMP_HEAP_BASE: u32 = 0xFFC8E000;
-pub const TD_SHIM_FREE_BASE: u32 = 0xFFCAE000;
-pub const TD_SHIM_METADATA_BASE: u32 = 0xFFCAF000;
-pub const TD_SHIM_IPL_BASE: u32 = 0xFFCB0000;
-pub const TD_SHIM_RESET_VECTOR_BASE: u32 = 0xFFFF8000;
+pub const TD_SHIM_SEC_CORE_INFO_OFFSET: u32 = 0xFFEFAC;
+pub const TD_SHIM_SEC_CORE_INFO_BASE: u32 = 0xFFFFFFAB;