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td-layout: load payload image into physical memory space #675

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td-layout: load payload image into physical memory space #675

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15abee1
td-shim: remove the FV header for payload image
gaojiaqi7 Mar 20, 2024
1c2cdf9
td-shim: use OVMF GUID table to find metadata offset
gaojiaqi7 Mar 20, 2024
cca148a
td-layout-config: load payload image into physical memory space
gaojiaqi7 Mar 20, 2024
1b71a3c
td-layout: update source code based on new layout
gaojiaqi7 Mar 20, 2024
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5 changes: 5 additions & 0 deletions devtools/td-layout-config/config_memory_exec.json
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Original file line number Diff line number Diff line change
Expand Up @@ -10,6 +10,11 @@
"size": "0x20000",
"type": "Memory"
},
{
"name": "ShimPayload",
"size": "0xC2D000",
"type": "Memory"
},
{
"name": "EventLog",
"size": "0x100000",
Expand Down
107 changes: 56 additions & 51 deletions devtools/td-layout-config/src/image.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -2,6 +2,9 @@ use serde::Deserialize;

use super::{layout::LayoutConfig, render};

const FIRMWARE_ROM_BASE: usize = 0xFF00_0000;
const FIRMWARE_ROM_SIZE: usize = 0x100_0000;

#[derive(Deserialize, Debug, PartialEq)]
struct ImageConfig {
#[serde(rename = "Config")]
Expand All @@ -28,60 +31,62 @@ pub fn parse_image(data: String) -> String {
let image_config = serde_json::from_str::<ImageConfig>(&data)
.expect("Content is configuration file is invalid");

let mut image_layout = LayoutConfig::new(0, 0x100_0000);
image_layout.reserve_low(
"Config",
parse_int::parse::<u32>(&image_config.config).unwrap() as usize,
"Reserved",
);
image_layout.reserve_low(
"Mailbox",
parse_int::parse::<u32>(&image_config.mailbox).unwrap() as usize,
"Reserved",
);
image_layout.reserve_low(
"TempStack",
parse_int::parse::<u32>(&image_config.temp_stack).unwrap() as usize,
"Reserved",
);
image_layout.reserve_low(
"TempHeap",
parse_int::parse::<u32>(&image_config.temp_heap).unwrap() as usize,
"Reserved",
);

image_layout.reserve_high(
"ResetVector",
parse_int::parse::<u32>(&image_config.reset_vector).unwrap() as usize,
"Reserved",
);
image_layout.reserve_high(
"Ipl",
parse_int::parse::<u32>(&image_config.bootloader).unwrap() as usize,
"Reserved",
);
let config_size = parse_int::parse::<u32>(&image_config.config).unwrap() as usize;
let mailbox_size = parse_int::parse::<u32>(&image_config.mailbox).unwrap() as usize;
let temp_stack_size = parse_int::parse::<u32>(&image_config.temp_stack).unwrap() as usize;
let temp_heap_size = parse_int::parse::<u32>(&image_config.temp_heap).unwrap() as usize;
let reset_vector_size = parse_int::parse::<u32>(&image_config.reset_vector).unwrap() as usize;
let ipl_size = parse_int::parse::<u32>(&image_config.bootloader).unwrap() as usize;
let metadata_size = parse_int::parse::<u32>(&image_config.metadata).unwrap() as usize;
let payload_size = parse_int::parse::<u32>(
&image_config
.builtin_payload
.unwrap_or_else(|| "0".to_string()),
)
.unwrap() as usize;
let td_info_size =
parse_int::parse::<u32>(&image_config.td_info.unwrap_or_else(|| "0".to_string())).unwrap()
as usize;

image_layout.reserve_high(
"Metadata",
parse_int::parse::<u32>(&image_config.metadata).unwrap() as usize,
"Reserved",
);

if let Some(td_info_config) = image_config.td_info {
image_layout.reserve_high(
"TdInfo",
parse_int::parse::<u32>(&td_info_config).unwrap() as usize,
"Reserved",
)
// Build firmware image layout
let image_size = config_size
+ reset_vector_size
+ mailbox_size
+ temp_heap_size
+ temp_stack_size
+ ipl_size
+ metadata_size
+ payload_size
+ td_info_size;
let mut image_layout = LayoutConfig::new(0, image_size);
image_layout.reserve_low("Config", config_size, "Image");
image_layout.reserve_low("Mailbox", mailbox_size, "Rom");
image_layout.reserve_low("TempStack", temp_stack_size, "Rom");
image_layout.reserve_low("TempHeap", temp_heap_size, "Rom");
image_layout.reserve_high("ResetVector", reset_vector_size, "Image");
image_layout.reserve_high("Ipl", ipl_size, "Image");
image_layout.reserve_high("Metadata", metadata_size, "Image");
if td_info_size != 0 {
image_layout.reserve_high("TdInfo", td_info_size, "Image")
}
if payload_size != 0 {
image_layout.reserve_high("Payload", payload_size, "Image")
}

if let Some(payload_config) = image_config.builtin_payload {
image_layout.reserve_high(
"Payload",
parse_int::parse::<u32>(&payload_config).unwrap() as usize,
"Reserved",
)
// Build ROM layout at memory space: 0xFF00_0000 - 0xFFFF_FFFF
// Payload image is not loaded into ROM space.
let mut rom_layout =
LayoutConfig::new(FIRMWARE_ROM_BASE, FIRMWARE_ROM_BASE + FIRMWARE_ROM_SIZE);
rom_layout.reserve_low("Config", config_size, "Rom");
rom_layout.reserve_low("Mailbox", mailbox_size, "Rom");
rom_layout.reserve_low("TempStack", temp_stack_size, "Rom");
rom_layout.reserve_low("TempHeap", temp_heap_size, "Rom");
rom_layout.reserve_high("ResetVector", reset_vector_size, "Rom");
rom_layout.reserve_high("Ipl", ipl_size, "Rom");
rom_layout.reserve_high("Metadata", metadata_size, "Rom");
if td_info_size != 0 {
rom_layout.reserve_high("TdInfo", td_info_size, "Rom")
}

render::render_image(&image_layout).expect("Render image layout failed!")
render::render_image(&image_layout, &rom_layout).expect("Render image layout failed!")
}
10 changes: 5 additions & 5 deletions devtools/td-layout-config/src/render.rs
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Expand Up @@ -9,7 +9,7 @@ use tera::{Context, Result, Tera};
use super::layout::{LayoutConfig, ENTRY_TYPE_FILTER};

/// Render image layout file.
pub fn render_image(image_layout: &LayoutConfig) -> Result<String> {
pub fn render_image(image_layout: &LayoutConfig, rom_layout: &LayoutConfig) -> Result<String> {
let mut tera = Tera::default();
tera.register_filter("format_hex", format_hex);
tera.register_filter("format_name", format_name);
Expand All @@ -19,12 +19,12 @@ pub fn render_image(image_layout: &LayoutConfig) -> Result<String> {
let mut context = Context::new();
context.insert("image_regions", image_layout.get_regions());
context.insert("image_size", &image_layout.get_top());
context.insert("rom_regions", &rom_layout.get_regions());
context.insert("rom_size", &(rom_layout.get_top() - rom_layout.get_base()));
// Image size - metadata pointer offset(0x20) - OVMF GUID table size(0x28) - SEC Core information size(0xC).
context.insert("sec_info_offset", &(image_layout.get_top() - 0x54));
context.insert(
"memory_offset",
&(u32::MAX as usize + 1 - &image_layout.get_top()),
);
context.insert("sec_info_base", &(rom_layout.get_top() - 0x54));
context.insert("rom_base", &rom_layout.get_base());
context.insert("entry_type_filter", ENTRY_TYPE_FILTER);
tera.render("image.rs", &context)
}
Expand Down
31 changes: 18 additions & 13 deletions devtools/td-layout-config/src/template/image.jinja
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Original file line number Diff line number Diff line change
Expand Up @@ -14,21 +14,26 @@ Image Layout
Image size: {{image_size|format_hex}} ({{image_size|filesizeformat}})
*/

// Image Layout Configuration
{%for i in image_regions%}
// Image configuration
pub const TD_SHIM_IMAGE_SIZE: u32 = {{image_size | format_hex }};
{%-for i in image_regions%}
pub const TD_SHIM_{{i.name_screaming_snake_case}}_OFFSET: u32 = {{i.region.start | format_hex }};
pub const TD_SHIM_{{i.name_screaming_snake_case}}_SIZE: u32 = {{i.region.end - i.region.start | format_hex }}; // {{i.region.end - i.region.start|filesizeformat}}
{%endfor%}
// Offset when Loading into Memory
pub const TD_SHIM_FIRMWARE_BASE: u32 = {{memory_offset | format_hex }};
pub const TD_SHIM_FIRMWARE_SIZE: u32 = {{image_size | format_hex }};
{%-endfor%}

// Size of regions
{%-for i in image_regions%}
pub const TD_SHIM_{{i.name_screaming_snake_case}}_SIZE: u32 = {{i.region.end - i.region.start | format_hex }};
{%-endfor%}

pub const TD_SHIM_FIRMWARE_BASE: u32 = {{rom_base | format_hex }};
pub const TD_SHIM_FIRMWARE_SIZE: u32 = {{rom_size | format_hex }};

// ROM configuration
{%-for i in rom_regions%}
pub const TD_SHIM_{{i.name_screaming_snake_case}}_BASE: u32 = {{i.region.start | format_hex }};
{%-endfor%}

// TD_SHIM_SEC_INFO_OFFSET equals to firmware size - metadata pointer offset -
// OVMF GUID table size - SEC Core information size.
pub const TD_SHIM_SEC_CORE_INFO_OFFSET: u32 = {{sec_info_offset | format_hex }};
pub const TD_SHIM_SEC_CORE_INFO_BASE: u32 = {{memory_offset + sec_info_offset | format_hex }};

// Base Address after Loaded into Memory
{%-for i in image_regions%}
pub const TD_SHIM_{{i.name_screaming_snake_case}}_BASE: u32 = {{memory_offset + i.region.start | format_hex }};
{%-endfor%}
pub const TD_SHIM_SEC_CORE_INFO_BASE: u32 = {{sec_info_base | format_hex }};
68 changes: 30 additions & 38 deletions td-layout/src/build_time.rs
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Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
// Copyright (c) 2021 - 2023 Intel Corporation
// Copyright (c) 2021 - 2024 Intel Corporation
//
// SPDX-License-Identifier: BSD-2-Clause-Patent

Expand All @@ -7,72 +7,64 @@
/*
Image Layout
+----------------------------------------+ <- 0x0
| CONFIG | (0x40000) 256 KB
| CONFIG | (0x40000) 256 kB
+----------------------------------------+ <- 0x40000
| MAILBOX | (0x1000) 4 KB
| MAILBOX | (0x1000) 4 kB
+----------------------------------------+ <- 0x41000
| TEMP_STACK | (0x20000) 128 KB
| TEMP_STACK | (0x20000) 128 kB
+----------------------------------------+ <- 0x61000
| TEMP_HEAP | (0x20000) 128 KB
| TEMP_HEAP | (0x20000) 128 kB
+----------------------------------------+ <- 0x81000
| FREE | (0x1000) 4 KB
+----------------------------------------+ <- 0x82000
| PAYLOAD | (0xC2D000) 12.18 MB
| FREE | (0x0) 0 B
+----------------------------------------+ <- 0x81000
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what is this?

| PAYLOAD | (0xC2E000) 12.18 MB
+----------------------------------------+ <- 0xCAF000
| METADATA | (0x1000) 4 KB
| METADATA | (0x1000) 4 kB
+----------------------------------------+ <- 0xCB0000
| IPL | (0x348000) 3.28 MB
+----------------------------------------+ <- 0xFF8000
| RESET_VECTOR | (0x8000) 32 KB
| RESET_VECTOR | (0x8000) 32 kB
+----------------------------------------+ <- 0x1000000
Image size: 0x1000000 (16 MB)
*/

// Image Layout Configuration

// Image configuration
pub const TD_SHIM_IMAGE_SIZE: u32 = 0x1000000;
pub const TD_SHIM_CONFIG_OFFSET: u32 = 0x0;
pub const TD_SHIM_CONFIG_SIZE: u32 = 0x40000; // 256 KB

pub const TD_SHIM_MAILBOX_OFFSET: u32 = 0x40000;
pub const TD_SHIM_MAILBOX_SIZE: u32 = 0x1000; // 4 KB

pub const TD_SHIM_TEMP_STACK_OFFSET: u32 = 0x41000;
pub const TD_SHIM_TEMP_STACK_SIZE: u32 = 0x20000; // 128 KB

pub const TD_SHIM_TEMP_HEAP_OFFSET: u32 = 0x61000;
pub const TD_SHIM_TEMP_HEAP_SIZE: u32 = 0x20000; // 128 KB

pub const TD_SHIM_FREE_OFFSET: u32 = 0x81000;
pub const TD_SHIM_FREE_SIZE: u32 = 0x1000; // 4 KB

pub const TD_SHIM_PAYLOAD_OFFSET: u32 = 0x82000;
pub const TD_SHIM_PAYLOAD_SIZE: u32 = 0xC2D000; // 12.18 MB

pub const TD_SHIM_PAYLOAD_OFFSET: u32 = 0x81000;
pub const TD_SHIM_METADATA_OFFSET: u32 = 0xCAF000;
pub const TD_SHIM_METADATA_SIZE: u32 = 0x1000; // 4 KB

pub const TD_SHIM_IPL_OFFSET: u32 = 0xCB0000;
pub const TD_SHIM_IPL_SIZE: u32 = 0x348000; // 3.28 MB

pub const TD_SHIM_RESET_VECTOR_OFFSET: u32 = 0xFF8000;
pub const TD_SHIM_RESET_VECTOR_SIZE: u32 = 0x8000; // 32 KB

// Offset when Loading into Memory
// Size of regions
pub const TD_SHIM_CONFIG_SIZE: u32 = 0x40000;
pub const TD_SHIM_MAILBOX_SIZE: u32 = 0x1000;
pub const TD_SHIM_TEMP_STACK_SIZE: u32 = 0x20000;
pub const TD_SHIM_TEMP_HEAP_SIZE: u32 = 0x20000;
pub const TD_SHIM_FREE_SIZE: u32 = 0x0;
pub const TD_SHIM_PAYLOAD_SIZE: u32 = 0xC2E000;
pub const TD_SHIM_METADATA_SIZE: u32 = 0x1000;
pub const TD_SHIM_IPL_SIZE: u32 = 0x348000;
pub const TD_SHIM_RESET_VECTOR_SIZE: u32 = 0x8000;

pub const TD_SHIM_FIRMWARE_BASE: u32 = 0xFF000000;
pub const TD_SHIM_FIRMWARE_SIZE: u32 = 0x1000000;

// TD_SHIM_SEC_INFO_OFFSET equals to firmware size - metadata pointer offset -
// OVMF GUID table size - SEC Core information size.
pub const TD_SHIM_SEC_CORE_INFO_OFFSET: u32 = 0xFFFFAC;
pub const TD_SHIM_SEC_CORE_INFO_BASE: u32 = 0xFFFFFFAC;

// Base Address after Loaded into Memory
// ROM configuration
pub const TD_SHIM_CONFIG_BASE: u32 = 0xFF000000;
pub const TD_SHIM_MAILBOX_BASE: u32 = 0xFF040000;
pub const TD_SHIM_TEMP_STACK_BASE: u32 = 0xFF041000;
pub const TD_SHIM_TEMP_HEAP_BASE: u32 = 0xFF061000;
pub const TD_SHIM_FREE_BASE: u32 = 0xFF081000;
pub const TD_SHIM_PAYLOAD_BASE: u32 = 0xFF082000;
pub const TD_SHIM_METADATA_BASE: u32 = 0xFFCAF000;
pub const TD_SHIM_IPL_BASE: u32 = 0xFFCB0000;
pub const TD_SHIM_RESET_VECTOR_BASE: u32 = 0xFFFF8000;

// TD_SHIM_SEC_INFO_OFFSET equals to firmware size - metadata pointer offset -
// OVMF GUID table size - SEC Core information size.
pub const TD_SHIM_SEC_CORE_INFO_OFFSET: u32 = 0xFFFFAC;
pub const TD_SHIM_SEC_CORE_INFO_BASE: u32 = 0xFFFFFFAC;
22 changes: 2 additions & 20 deletions td-layout/src/memslice.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,7 @@ pub enum SliceType {
Config,
/// The `TD_HOB` region in image file
TdHob,
/// The `Payload and Metadata` region in image file
/// The `Payload Image` region in runtime memory layout
ShimPayload,
/// The `TD_MAILBOX` region in image file
MailBox,
Expand Down Expand Up @@ -69,10 +69,6 @@ pub fn get_mem_slice<'a>(t: SliceType) -> &'a [u8] {
TD_SHIM_CONFIG_BASE as *const u8,
TD_SHIM_CONFIG_SIZE as usize,
),
SliceType::ShimPayload => core::slice::from_raw_parts(
TD_SHIM_PAYLOAD_BASE as *const u8,
TD_SHIM_PAYLOAD_SIZE as usize,
),
SliceType::MailBox => core::slice::from_raw_parts(
TD_SHIM_MAILBOX_BASE as *const u8,
TD_SHIM_MAILBOX_SIZE as usize,
Expand All @@ -94,7 +90,7 @@ pub unsafe fn get_mem_slice_mut<'a>(t: SliceType) -> &'a mut [u8] {
TD_SHIM_MAILBOX_BASE as *const u8 as *mut u8,
TD_SHIM_MAILBOX_SIZE as usize,
),
SliceType::Config | SliceType::ShimPayload => {
SliceType::Config => {
panic!("get_mem_slice_mut: read only")
}
_ => panic!("get_mem_slice_mut: not support"),
Expand All @@ -111,12 +107,6 @@ mod test {
assert_eq!(config.len(), TD_SHIM_CONFIG_SIZE as usize);
}

#[test]
fn test_get_mem_slice_with_type_builtin_payload() {
let payload = get_mem_slice(SliceType::ShimPayload);
assert_eq!(payload.len(), TD_SHIM_PAYLOAD_SIZE as usize);
}

#[test]
#[should_panic(expected = "get_mem_slice: not support")]
fn test_get_mem_slice_with_type_payload() {
Expand Down Expand Up @@ -153,14 +143,6 @@ mod test {
assert_eq!(mailbox.len(), TD_SHIM_MAILBOX_SIZE as usize);
}

#[test]
#[should_panic(expected = "get_mem_slice_mut: read only")]
fn test_get_mem_slice_mut_with_type_builtin_payload() {
unsafe {
get_mem_slice_mut(SliceType::ShimPayload);
}
}

#[test]
#[should_panic(expected = "get_mem_slice_mut: read only")]
fn test_get_mem_slice_mut_with_type_config() {
Expand Down
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