test: Add test case for MSR Read&Write

tests/test-td-payload/config/test_config_1.json

@@ -142,5 +142,10 @@
                   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],   
         "result": "None",
         "run": true 
+    },
+    "tcs020": {
+        "name": "testmsrrw",     
+        "result": "None",
+        "run": true 
     }
 }

tests/test-td-payload/config/test_config_2.json

@@ -146,5 +146,10 @@
                   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],   
         "result": "None",
         "run": true 
+    },
+    "tcs020": {
+        "name": "testmsrrw",     
+        "result": "None",
+        "run": true 
     }
 }

tests/test-td-payload/config/test_config_3.json

@@ -146,5 +146,10 @@
                   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],   
         "result": "None",
         "run": true 
+    },
+    "tcs020": {
+        "name": "testmsrrw",     
+        "result": "None",
+        "run": true 
     }
 }

tests/test-td-payload/config/test_config_4.json

@@ -146,5 +146,10 @@
                   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],   
         "result": "None",
         "run": true 
+    },
+    "tcs020": {
+        "name": "testmsrrw",     
+        "result": "None",
+        "run": true 
     }
 }

tests/test-td-payload/config/test_config_5.json

@@ -146,5 +146,10 @@
                   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],   
         "result": "None",
         "run": true 
+    },
+    "tcs020": {
+        "name": "testmsrrw",     
+        "result": "None",
+        "run": true 
     }
 }

tests/test-td-payload/src/main.rs

@@ -15,6 +15,7 @@ mod testcetshstk;
 mod testiorw32;
 mod testiorw8;
 mod testmemmap;
+mod testmsrrw;
 mod teststackguard;
 mod testtdinfo;
 mod testtdreport;
@@ -39,6 +40,7 @@ use crate::testcetshstk::TestCetShstk;
 use crate::testiorw32::Tdiorw32;
 use crate::testiorw8::Tdiorw8;
 use crate::testmemmap::MemoryMap;
+use crate::testmsrrw::Tdmsrrw;
 use crate::teststackguard::TestStackGuard;
 use crate::testtdinfo::Tdinfo;
 use crate::testtdreport::Tdreport;
@@ -79,6 +81,7 @@ pub struct TestCases {
     pub tcs017: Option<TestStackGuard>,
     pub tcs018: Option<TestCetShstk>,
     pub tcs019: Option<TestCetIbt>,
+    pub tcs020: Tdmsrrw,
 }
 
 pub const CFV_FFS_HEADER_TEST_CONFIG_GUID: Guid = Guid::from_fields(
@@ -262,6 +265,10 @@ extern "C" fn main() -> ! {
         }
     }
 
+    if tcs.tcs020.run {
+        ts.testsuite.push(Box::new(tcs.tcs020));
+    }
+
     // run the TestSuite which contains the test cases
     print!("---------------------------------------------\n");
     print!("Start to run tests.\n");

tests/test-td-payload/src/testmsrrw.rs

@@ -0,0 +1,100 @@
+// Copyright (c) 2022 Intel Corporation
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+
+#![no_std]
+extern crate alloc;
+
+use crate::lib::{TestCase, TestResult};
+use alloc::string::String;
+use core::ffi::c_void;
+use tdx_tdcall::tdx;
+
+use serde::{Deserialize, Serialize};
+
+/**
+ * Test tdvmcall read/write MSR
+ */
+#[derive(Debug, Serialize, Deserialize)]
+pub struct Tdmsrrw {
+    pub name: String,
+    pub result: TestResult,
+    pub run: bool,
+}
+
+impl Tdmsrrw {
+    fn test(&mut self) -> TestResult {
+        const APIC_SVR_MSR: u32 = 0x80f; // APIC Spurious Vector Register MSR address
+
+        // Read the current value of the APIC SVR MSR
+        match tdx::tdvmcall_rdmsr(APIC_SVR_MSR) {
+            Ok(read1) => {
+                // Attempt to write the incremented value back to the APIC SVR MSR
+                if tdx::tdvmcall_wrmsr(APIC_SVR_MSR, read1 + 1).is_err() {
+                    log::info!("Failed to write MSR 0x{:x}", APIC_SVR_MSR);
+                    return TestResult::Fail;
+                }
+
+                // Read the value again to verify the write operation
+                match tdx::tdvmcall_rdmsr(APIC_SVR_MSR) {
+                    Ok(read2) if read1 + 1 == read2 => TestResult::Pass,
+                    Ok(read2) => {
+                        log::info!(
+                            "Mismatch after write: expected {:?}, actual {:?}",
+                            read1 + 1,
+                            read2
+                        );
+                        TestResult::Fail
+                    }
+                    Err(_) => {
+                        log::info!("Failed to read MSR 0x{:x}", APIC_SVR_MSR);
+                        TestResult::Fail
+                    }
+                }
+            }
+            Err(_) => {
+                log::info!("Failed to read MSR 0x{:x}", APIC_SVR_MSR);
+                TestResult::Fail
+            }
+        }
+    }
+}
+
+/**
+ * Implement the TestCase trait for Tdmsrrw
+ */
+impl TestCase for Tdmsrrw {
+    /**
+     * set up the Test case of Tdmsrrw
+     */
+    fn setup(&mut self) {
+        self.result = TestResult::Fail;
+    }
+
+    /**
+     * run the test case
+     * mmio read/write vsock device
+     */
+    fn run(&mut self) {
+        self.result = self.test();
+    }
+
+    /**
+     * Tear down the test case.
+     */
+    fn teardown(&mut self) {}
+
+    /**
+     * get the name of the test case.
+     */
+    fn get_name(&mut self) -> String {
+        String::from(&self.name)
+    }
+
+    /**
+     * get the result of the test case.
+     */
+    fn get_result(&mut self) -> TestResult {
+        self.result
+    }
+}