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[API][Backend][0.3] Unified simulation and implementation interface f…
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…or HeteroCL (#162)

* [API] Enable building a function directly from IR (#133)

* add a pass for building a function directly from IR

* remove redundant print statement

* [API] Enable select API to accept Python expressions

* [API] Fixed incorrect casting for select in CastRemover

* [API][Backend] Streaming and OpenCL Backends (#138)

* add sdaccel, aocl for heterocl

* fpga

* Create codeanalys_openclc.cc

* Update target.py

* run

* can run successfully

* Create codegen_opencl.cc

* now

* all done

* Update codegen_sdaccel.cc

* Update codegen_sdaccel.cc

* 	modified:   python/heterocl/tvm/target.py

* 	new file:   samples/ppac/gemm/csrcPrint.py
	new file:   samples/ppac/gemm/data.py
	new file:   samples/ppac/gemm/gemm_ppac.py
	new file:   samples/ppac/gemm/headcode.txt
	new file:   samples/ppac/gemm/ppac_common.py
	new file:   tvm/src/codegen/build_ppac.cc
	new file:   tvm/src/codegen/codegen_rv64_ppac.cc
	new file:   tvm/src/codegen/codegen_rv64_ppac.h

* all

* remove tvm check code from kernel

* opencl-backend

* all

* fix ppac module build

* support ppac MVPb pragma

* fix ignoring ppac pragma in cpu backend

* opencl-backend

* aocl-backend

* move ppac codegen to ppac folder; fix argument name with merlinc analyser

* discard the new for-loop type; include ppac in hlib

* discard some previous changes

* Use int64_t as return type of GeMM on ppac

* [add] codegenc kernedef + stream init

* [add] var_shape_map

* [update] kerneldef struct shape

* [update] use noderef and restore

* [fix] return op

* [add] hcl device & kernelstmt printer

* [fix] def workaround

* [update] stream example

* [add] stream expr & stmt ir

* [fix] kernel arg location for stream

* opt1

* opencl-general

* new-version

* no bug

* a

* test+unroll+pipeline

* pragma

* new

* type has fixed

* new_test

* test_reorder_split_fuse

* target

* order

* simplified by rui

* analysis

* bug fixed

* [delete] all of the code about opencl

* [ADD] new opencl back-end including xilinx & intel

* fixed __local

* fixed data_type for xilinx opencl

* add makefile for SDAccel_runtime

* add the runtime for sdaccel

* create the sdaccel host

* fixed the indent problem partly

* test the zhang-05 server

* add indent to the host.cpp

* automatically generate makefile

* delete common folder from opencl

* add shmat to sdaccel runtime

* fixed bug for sdaccel runtime seg fault

* fixed the bug of host.cpp multiple

* fixed host.cpp multiple bug

* fixed endif for makefile

* modify sdaccel_sw_emu -> sdaccel_csim

* fix the __local and __global for intel opencl back-end

* Fix the arbitrary integer precision for aocl

* [add] ir visitor & functor for codegen

* [add] aocl stream codegen

* [add] aocl stream support

* [fix] aocl type conversion

* [fix] aocl channel syntax

* [add] sch.stream_to

* [fix] add stream annotation

* [add] host device codegen

* [add] stream ir mutator

* [Add] Interface prag,a for SDx sim

* [add] host xcel codegen

* [update] build interface

* [update] new build interface

* [fix] temp update

* [update] stream example

* [add] rocc-ppac sim

* [rm] submodule

* [update] rocc ppac hlib

* [add] unified sim & kernel updater

* re-organize build common util

* [update] stream in codegen c

* [update] codegen construct for streaming

* [update] code post-processing

* [fix] test cases

* [fix] python compatibility

* [update] future

* [fix] metaclass

* [fix] test import issue

* Revert "[API][Backend] Streaming and OpenCL Backends (#138)" (#139)

This reverts commit 2c75344.

* [API] Remove support for Python 2 (#143)

* remove support for Python 2

* switch from Python 3.7 to 3.6

* [Backend] Fix LLVM CodeGen for intrinsics (#147)

* Fix llvm codegen for instrinsic log, pow, and sqrt

* fix test case

* [Backend] Fix LLVM power intrinsic with large integer (#151)

* fix llvm power with large integer

* fix test case

* [API] Fix Wrong Index Calculation in API reuse_at (#156)

* codegen interface

* tool config + fixed codegen issue

* update tempaltes

* hcl vitis runtime

* vivado hls sim works

* vitis flow

* aocl flow

* aocl dtype

* clean up gemm

* fix and systolic array example

* clean up

Co-authored-by: Yi-Hsiang (Sean) Lai <[email protected]>
Co-authored-by: Shaojie Xiang <[email protected]>
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@hecmay @seanlatias
3 people authored Mar 28, 2020
1 parent 4ee8384 commit d678876
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Showing 61 changed files with 3,344 additions and 2,377 deletions.
52 changes: 37 additions & 15 deletions python/heterocl/devices.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -49,11 +49,12 @@ def __repr__(self):
str(self.options)

tool_table = {
"aws_f1" : tool("sdaccel", *option_table["sdaccel"]),
"aws_f1" : tool("sdaccel", *option_table["sdaccel"]),
"zc706" : tool("vivado_hls", *option_table["vivado_hls"]),
"ppac" : tool("rocket", *option_table["rocket"]),
"stratix10_sx": tool("aocl", *option_table["aocl"]),
"llvm" : tool("llvm", *option_table["llvm"])
"ppac" : tool("rocket", *option_table["rocket"]),
"vlab" : tool("aocl", *option_table["aocl"]),
"stratix10_sx": tool("aocl", *option_table["aocl"]),
"llvm" : tool("llvm", *option_table["llvm"])
}

class Device(object):
Expand Down Expand Up @@ -83,7 +84,7 @@ def __getattr__(self, key):

def set_lang(self, lang):
assert lang in \
["opencl", "hlsc", "c", "opengl", "merlinc", "cuda", "metal"], \
["xocl", "aocl", "vhls", "ihls", "merlinc", "cuda"], \
"unsupported lang sepc " + lang
self.impls["lang"] = lang
return self
Expand Down Expand Up @@ -134,10 +135,11 @@ def __repr__(self):
return "pim-" + str(self.model)

dev_table = {
"aws_f1" : [CPU("intel", "e5"), FPGA("xilinx", "xcvu19p")],
"zc706" : [CPU("arm", "a9"), FPGA("xilinx", "xc7z045")],
"rocc-ppac" : [CPU("riscv", "riscv"), PIM("ppac", "ppac")],
"stratix10_sx": [CPU("arm", "a53"), FPGA("intel", "stratix10_gx")]
"aws_f1" : [CPU("intel", "e5"), FPGA("xilinx", "xcvu19p")],
"vlab" : [CPU("intel", "e5"), FPGA("intel", "arria10")],
"zc706" : [CPU("arm", "a9"), FPGA("xilinx", "xc7z045")],
"rocc-ppac" : [CPU("riscv", "riscv"), PIM("ppac", "ppac")],
"stratix10_sx" : [CPU("arm", "a53"), FPGA("intel", "stratix10_gx")]
}

class env(type):
Expand All @@ -156,12 +158,16 @@ class env(type):
def __getattr__(cls, key):
if key == "aws_f1":
devs = dev_table[key]
host = devs[0].set_lang("opencl")
xcel = devs[1].set_lang("hlsc")
host = devs[0].set_lang("xocl")
xcel = devs[1].set_lang("vhls")
elif key == "zc706":
devs = dev_table[key]
host = devs[0].set_lang("hlsc")
xcel = devs[1].set_lang("hlsc")
host = devs[0].set_lang("vhls")
xcel = devs[1].set_lang("vhls")
elif key == "vlab":
devs = dev_table[key]
host = devs[0].set_lang("aocl")
xcel = devs[1].set_lang("aocl")
elif key == "llvm":
devs = None
host = None
Expand All @@ -187,10 +193,26 @@ def __init__(self, name, devs, host, xcel, tool):
self.cpu = host
if isinstance(xcel, FPGA):
self.fpga = xcel
elif isinstance(xcel, PIM) and \
xcel.model == "ppac":
elif isinstance(xcel, PIM) and xcel.model == "ppac":
self.ppac = xcel

def config(self, compile=None, mode=None, backend=None):
if compile: # check the backend
assert compile in option_table.keys(), \
"not support tool " + compile
self.tool = tool(compile, *option_table[compile])

if mode: # check tool mode
modes = ["sw_sim", "hw_sim", "hw_exe", "debug"]
assert mode in modes, \
"supported tool mode: " + str(modes)
self.tool.mode = mode

if backend: # set up backend lang
assert backend in ["vhls", "aocl", "sdaccel"], \
"not support backend lang " + backend
self.xcel.lang = backend

def __getattr__(self, key):
""" return tool options """
return self.tool.__getattr__(key)
Expand Down
19 changes: 15 additions & 4 deletions python/heterocl/dsl.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -323,7 +323,7 @@ def break_():
Stage.get_current().emit(_make.Break())
Stage.get_current().has_break = True

def def_(shapes, dtypes=None, ret_dtype=None, name=None):
def def_(shapes, dtypes=None, ret_dtype=None, name=None, arg_names=None):
"""
Define a HeteroCL function from a Python function.
Expand Down Expand Up @@ -386,25 +386,33 @@ def ret_add(A, B, x):
C = hcl.compute((10,), lambda x: ret_add(A, B, x))
D = hcl.compute((10,), lambda x: ret_add(A, C, x))
"""
def decorator(fmodule, shapes=shapes, dtypes=dtypes, ret_dtype=ret_dtype, name=name):
def decorator(fmodule, shapes=shapes, dtypes=dtypes, ret_dtype=ret_dtype, name=name, arg_names=arg_names):
name = name if name is not None else fmodule.__name__
code = fmodule.__code__
names = code.co_varnames
if arg_names is not None:
names = list(names)
for i in range(len(arg_names)):
names[i] = arg_names[i]
names = tuple(names)
nargs = code.co_argcount

with Stage(name) as s:
# prepare names
new_names = [s.name_with_prefix + "." + name_ for name_ in names]
# prepare dtypes
hcl_dtypes = []
if dtypes is None:
dtypes = []
for name_ in new_names:
dtypes.append(util.get_tvm_dtype(None, name_))
hcl_dtypes.append(util.get_dtype(None, name_))
elif isinstance(dtypes, list):
if len(dtypes) != nargs:
raise APIError("The number of data types does not match the of arguments")
for (name_, dtype_) in zip(new_names, dtypes):
dtypes.append(util.get_tvm_dtype(dtype_, name_))
hcl_dtypes.append(util.get_dtype(dtype_, name_))
dtypes = dtypes[int(len(dtypes)/2):]
else:
dtype = util.get_tvm_dtype(dtypes)
Expand All @@ -416,22 +424,24 @@ def decorator(fmodule, shapes=shapes, dtypes=dtypes, ret_dtype=ret_dtype, name=n
inputs = []
inputs_tvm = []
arg_shapes, arg_dtypes, arg_tensors = [], [], []
for shape, name_, dtype in zip(shapes, new_names, dtypes):
for shape, name_, dtype, htype in zip(shapes, new_names, dtypes, hcl_dtypes):
if shape == ():
var_ = placeholder((), name_, dtype)
inputs.append(var_)
inputs_tvm.append(var_.var)
arg_shapes.append([1])
arg_dtypes.append(dtype)
else: # tensor inputs (new bufs)
placeholder_ = placeholder(shape, name_, dtype)
placeholder_ = placeholder(shape, name_, htype)
inputs.append(placeholder_)
inputs_tvm.append(placeholder_.buf.data)
arg_shapes.append(list(shape))
arg_dtypes.append(dtype)
arg_tensors.append(placeholder_.op)

s.ret_dtype = ret_dtype
s._module = True
s._inputs = inputs
fmodule(*inputs)
lhs = []
for tensor in s.lhs_tensors:
Expand All @@ -441,6 +451,7 @@ def decorator(fmodule, shapes=shapes, dtypes=dtypes, ret_dtype=ret_dtype, name=n
pass
ret_void = _make.UIntImm("uint1", 0) if s.has_return else _make.UIntImm("uint1", 1)
body = s.pop_stmt()

s.stmt_stack.append([])
s.emit(_make.KernelDef(inputs_tvm, arg_shapes, arg_dtypes, arg_tensors,
body, ret_void, ret_dtype, name, []))
Expand Down
199 changes: 110 additions & 89 deletions python/heterocl/tools.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,105 +4,126 @@
model_table = {
"xilinx" : ["fpga_xc7z045", "fpga_xcvu19p"],
"intel" : ["cpu_e5", "cpu_i7", "fpga_stratix10_gx",
"fpga_stratix10_dx", "fpga_stratix10_mx"],
"fpga_stratix10_dx", "fpga_stratix10_mx", "fpga_arria10"],
"arm" : ["cpu_a7", "cpu_a9", "cpu_a53"],
"riscv" : ["cpu_riscv"]
}

option_table = {
"llvm" : ("llvm_sim", {"version" : "6.0.0"}),
"sdaccel" : ("sw_emu", {"version" : "2017.1", "clock" : "1"}),
"vivado_hls" : ("csim", {"version" : "2017.1"}),
"rocket" : ("source", {"RISCV" : ""}),
"llvm" : ("sw_sim", {"version" : "6.0.0"}),
"sdaccel" : ("sw_sim", {"version" : "2017.1", "clock" : "1"}),
"sdsoc" : ("sw_sim", {"version" : "2017.1", "clock" : "1"}),
"vitis" : ("sw_sim", {"version" : "2019.2", "clock" : "1"}),
"vivado_hls" : ("sw_sim", {"version" : "2017.1"}),
"rocket" : ("debug", {"RISCV" : ""}),

# refer to xilinx2016_1/ug904-vivado-implementation.pdf
"vivado" : ("pnr",
{"version" : "2017.1",
"logic" : ["Default", "Explore", "ExploreSequentialArea", "AddRemap", "ExploreArea"],
"placement" : ["Default", "Explore", "ExtraNetDelay_high", "ExtraNetDelay_medium", "ExtraNetDelay_low", "ExtraPostPlacementOpt", "WLDrivenBlockPlacement", "LateBlockPlacement", "AltSpreadLogic_low", "AltSpreadLogic_medium", "AltSpreadLogic_high"],
"routing" : ["Default", "Explore", "HigherDelayCost"],
"fanout_opt" : ["on", "off"],
"placement_opt" : ["on", "off"],
"critical_cell_opt" : ["on", "off"],
"critical_pin_opt" : ["on", "off"],
"retime" : ["on", "off"],
"rewire" : ["on", "off"],
}),
{"version" : "2017.1",
"logic" : [
"Default",
"Explore",
"ExploreSequentialArea",
"AddRemap",
"ExploreArea"],
"placement" : [
"Default",
"Explore",
"ExtraNetDelay_high",
"ExtraNetDelay_medium",
"ExtraNetDelay_low",
"ExtraPostPlacementOpt",
"WLDrivenBlockPlacement",
"LateBlockPlacement",
"AltSpreadLogic_low",
"AltSpreadLogic_medium",
"AltSpreadLogic_high"],
"routing" : [
"Default",
"Explore",
"HigherDelayCost"],
"fanout_opt" : ["on", "off"],
"placement_opt" : ["on", "off"],
"critical_cell_opt" : ["on", "off"],
"critical_pin_opt" : ["on", "off"],
"retime" : ["on", "off"],
"rewire" : ["on", "off"],
}),

"quartus" : ("pnr",
{"version" : "17.1",
"auto_dsp_recognition" : ['On', 'Off'],
"disable_register_merging_across_hierarchies": ['On', 'Off', 'Auto'],
"mux_restructure" : ['On', 'Off', 'Auto'],
"optimization_technique" : ['Area', 'Speed', 'Balanced'],
"synthesis_effort" : ['Auto', 'Fast'],
"synth_timing_driven_synthesis" : ['On', 'Off'],
"fitter_aggressive_routability_optimization" : ['Always', 'Automatically', 'Never'],
"fitter_effort" : ['Standard Fit', 'Auto Fit'],
"remove_duplicate_registers" : ['On', 'Off'],
"physical_synthesis" : ['On', 'Off'],
"adv_netlist_opt_synth_wysiwyg_remap" : ['On', 'Off'],
"allow_any_ram_size_for_recognition" : ['On', 'Off'],
"allow_any_rom_size_for_recognition" : ['On', 'Off'],
"allow_any_shift_register_size_for_recognition" : ['On', 'Off'],
"allow_power_up_dont_care" : ['On', 'Off'],
"allow_shift_register_merging_across_hierarchies" : ["Always", "Auto", "Off"],
"allow_synch_ctrl_usage" : ['On', 'Off'],
"auto_carry_chains" : ['On', 'Off'],
"auto_clock_enable_recognition" : ['On', 'Off'],
"auto_dsp_recognition" : ['On', 'Off'],
"auto_enable_smart_compile" : ['On', 'Off'],
"auto_open_drain_pins" : ['On', 'Off'],
"auto_ram_recognition" : ['On', 'Off'],
"auto_resource_sharing" : ['On', 'Off'],
"auto_rom_recognition" : ['On', 'Off'],
"auto_shift_register_recognition" : ["Always", "Auto", "Off"],
"disable_register_merging_across_hierarchies" : ["Auto", "On", "Off"],
"enable_state_machine_inference" : ['On', 'Off'],
"force_synch_clear" : ['On', 'Off'],
"ignore_carry_buffers" : ['On', 'Off'],
"ignore_cascade_buffers" : ['On', 'Off'],
"ignore_max_fanout_assignments" : ['On', 'Off'],
"infer_rams_from_raw_logic" : ['On', 'Off'],
"mux_restructure" : ["Auto", "On", "Off"],
"optimization_technique" : ["Area", "Balanced", "Speed"],
"optimize_power_during_synthesis" : ["Extra effort", "Normal compilation", "Off"],
"remove_duplicate_registers" : ['On', 'Off'],
"shift_register_recognition_aclr_signal" : ['On', 'Off'],
"state_machine_processing" :
["Auto", "Gray", "Johnson, Minimal Bits", "One-Hot", "Sequential", "User-Encoded"],
"strict_ram_recognition" : ['On', 'Off'],
"synthesis_effort" : ["Auto", "Fast"],
"synthesis_keep_synch_clear_preset_behavior_in_unmapper" : ['On', 'Off'],
"synth_resource_aware_inference_for_block_ram" : ['On', 'Off'],
"synth_timing_driven_synthesis" : ['On', 'Off'],
"alm_register_packing_effort" : ["High", "Low", "Medium"],
"auto_delay_chains" : ['On', 'Off'],
"auto_delay_chains_for_high_fanout_input_pins" : ["On", "Off"],
"eco_optimize_timing" : ["On", "Off"],
"final_placement_optimization" : ["Always", "Automatically", "Never"],
"fitter_aggressive_routability_optimization" : ["Always", "Automatically", "Never"],
"fitter_effort" : ["Standard Fit", "Auto Fit"],
"optimize_for_metastability" : ["On", "Off"],
"optimize_hold_timing" : ["All Paths", "IO Paths and Minimum TPD Paths", "Off"],
"optimize_ioc_register_placement_for_timing" :
["Normal", "Off", "Pack All IO Registers"],
"optimize_multi_corner_timing" : ['On', 'Off'],
"optimize_power_during_fitting" : ["Extra effort", "Normal compilation", "Off"],
"physical_synthesis" : ['On', 'Off'],
"placement_effort_multiplier" : [0.2, 0.5, 1.0, 2.0, 3.0, 4.0],
"programmable_power_technology_setting" : ["Automatic", "Force All Tiles with Failing Timing Paths to High Speed", "Force All Used Tiles to High Speed", "Minimize Power Only"],
"qii_auto_packed_registers" : ["Auto", "Minimize Area", "Minimize Area with Chains", "Normal", "Off", "Sparse", "Sparse Auto"],
"router_clocking_topology_analysis" : ['On', 'Off'],
"router_lcell_insertion_and_logic_duplication" : ["Auto", "On", "Off"],
"router_register_duplication" : ["Auto", "On", "Off"],
"router_timing_optimization_level" : ["MINIMUM", "Normal", "MAXIMUM"],
"seed" : (1, 5),
"tdc_aggressive_hold_closure_effort" : ['On', 'Off'],
"allow_register_retiming" : ['On', 'Off']}),
{"version" : "17.1",
"auto_dsp_recognition" : ['On', 'Off'],
"disable_register_merging_across_hierarchies" : ['On', 'Off', 'Auto'],
"mux_restructure" : ['On', 'Off', 'Auto'],
"optimization_technique" : ['Area', 'Speed', 'Balanced'],
"synthesis_effort" : ['Auto', 'Fast'],
"synth_timing_driven_synthesis" : ['On', 'Off'],
"fitter_aggressive_routability_optimization" : ['Always', 'Automatically', 'Never'],
"fitter_effort" : ['Standard Fit', 'Auto Fit'],
"remove_duplicate_registers" : ['On', 'Off'],
"physical_synthesis" : ['On', 'Off'],
"adv_netlist_opt_synth_wysiwyg_remap" : ['On', 'Off'],
"allow_any_ram_size_for_recognition" : ['On', 'Off'],
"allow_any_rom_size_for_recognition" : ['On', 'Off'],
"allow_any_shift_register_size_for_recognition" : ['On', 'Off'],
"allow_power_up_dont_care" : ['On', 'Off'],
"allow_shift_register_merging_across_hierarchies" : ["Always", "Auto", "Off"],
"allow_synch_ctrl_usage" : ['On', 'Off'],
"auto_carry_chains" : ['On', 'Off'],
"auto_clock_enable_recognition" : ['On', 'Off'],
"auto_dsp_recognition" : ['On', 'Off'],
"auto_enable_smart_compile" : ['On', 'Off'],
"auto_open_drain_pins" : ['On', 'Off'],
"auto_ram_recognition" : ['On', 'Off'],
"auto_resource_sharing" : ['On', 'Off'],
"auto_rom_recognition" : ['On', 'Off'],
"auto_shift_register_recognition" : ["Always", "Auto", "Off"],
"disable_register_merging_across_hierarchies" : ["Auto", "On", "Off"],
"enable_state_machine_inference" : ['On', 'Off'],
"force_synch_clear" : ['On', 'Off'],
"ignore_carry_buffers" : ['On', 'Off'],
"ignore_cascade_buffers" : ['On', 'Off'],
"ignore_max_fanout_assignments" : ['On', 'Off'],
"infer_rams_from_raw_logic" : ['On', 'Off'],
"mux_restructure" : ["Auto", "On", "Off"],
"optimization_technique" : ["Area", "Balanced", "Speed"],
"optimize_power_during_synthesis" : ["Extra effort", "Normal compilation", "Off"],
"remove_duplicate_registers" : ['On', 'Off'],
"shift_register_recognition_aclr_signal" : ['On', 'Off'],
"state_machine_processing" : ["Auto", "Gray",
"Johnson, Minimal Bits", "One-Hot", "Sequential", "User-Encoded"],
"strict_ram_recognition" : ['On', 'Off'],
"synthesis_effort" : ["Auto", "Fast"],
"synthesis_keep_synch_clear_preset_behavior_in_unmapper" : ['On', 'Off'],
"synth_resource_aware_inference_for_block_ram" : ['On', 'Off'],
"synth_timing_driven_synthesis" : ['On', 'Off'],
"alm_register_packing_effort" : ["High", "Low", "Medium"],
"auto_delay_chains" : ['On', 'Off'],
"auto_delay_chains_for_high_fanout_input_pins" : ["On", "Off"],
"eco_optimize_timing" : ["On", "Off"],
"final_placement_optimization" : ["Always", "Automatically", "Never"],
"fitter_aggressive_routability_optimization" : ["Always", "Automatically", "Never"],
"fitter_effort" : ["Standard Fit", "Auto Fit"],
"optimize_for_metastability" : ["On", "Off"],
"optimize_hold_timing" : ["All Paths", "IO Paths and Minimum TPD Paths", "Off"],
"optimize_ioc_register_placement_for_timing" : ["Normal", "Off", "Pack All IO Registers"],
"optimize_multi_corner_timing" : ['On', 'Off'],
"optimize_power_during_fitting" : ["Extra effort", "Normal compilation", "Off"],
"physical_synthesis" : ['On', 'Off'],
"placement_effort_multiplier" : [0.2, 0.5, 1.0, 2.0, 3.0, 4.0],
"programmable_power_technology_setting" : ["Automatic",
"Force All Tiles with Failing Timing Paths to High Speed",
"Force All Used Tiles to High Speed", "Minimize Power Only"],
"qii_auto_packed_registers" : ["Auto", "Minimize Area",
"Minimize Area with Chains", "Normal", "Off", "Sparse", "Sparse Auto"],
"router_clocking_topology_analysis" : ['On', 'Off'],
"router_lcell_insertion_and_logic_duplication" : ["Auto", "On", "Off"],
"router_register_duplication" : ["Auto", "On", "Off"],
"router_timing_optimization_level" : ["MINIMUM", "Normal", "MAXIMUM"],
"seed" : (1, 5),
"tdc_aggressive_hold_closure_effort" : ['On', 'Off'],
"allow_register_retiming" : ['On', 'Off']}),

"aocl" : ("emu", {"version" : "17.0",
"clokc" : 1.5,
})
"aocl" : ("sw_sim", {"version" : "17.0", "clock" : "1.5"})
}

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