mediatek: add support for Adtran SmartRG Bonanza Peak series

The Bonanza Peak series are a couple of MT7986-powered 2.5 GBit/s Wi-Fi 6 residential gateway, access point and mesh router products. All of them come with an eMMC to boot from, are powered via USB-C and got a USB 3.0 type-A port. All of them got a Dialog (Renesas) DA14531 Bluetooth module connected via UART. If the device was previously running stock firmware, the BT chip's internal flash has been loaded with firmware and it can be attached using hciattach when using OpenWrt. SOC: MediaTek MT7986A RAM: 2 GiB DDR4 eMMC: 8 GiB Bluetooth: BLE5 (DA14531) Serial: 3.3V level, 115200 8n1 on 4-pin connector * SDG-8612 - Dual-band RJ-45 gateway 2x 2.5G MaxLinear PHY for WAN port 3x 1GE LAN ports via MT7531 switch * SDG-8614 - Dual-band SFP gateway 1x SFP cage with up to 2.5G speed 1x 2.5G MaxLinear PHY for LAN port 3x 1GE LAN ports via MT7531 switch * SDG-8622 - Tri-band mesh router 2x 2.5G MaxLinear PHY The MT7986 2G and 5G are used as 2G and 5G high band. There’s a MT7915 PCIe card for 5G low band. * SDG-8632 - Tri-band mesh router with 6 GHz 2x 2.5G MaxLinear PHY The MT7986 serves the 2G and 6G bands. There’s a MT7915 PCIe card for 5G. Installation via U-Boot serial console: 0. setup TFTP server with IP 192.168.1.10/24, place initramfs image renamed to openwrt.XXX where XXX is the internal product number: SDG-8612: XXX = 412 SDG-8614: XXX = 414 SDG-8622: XXX = 422 SDG-8632: XXX = 432 1. connect to the serial console and power on the device. Interrupt the bootloader by pressing 'st' 2. setenv boot_mode openwrt ; saveenv 3. run boot1 Load firmware via TFTP and write to flash 4. run boot2 Now OpenWrt initramfs should boot 5. upload sysupgrade.bin via scp to /tmp 6. sysupgrade Signed-off-by: Daniel Golle <[email protected]>
csharper2005 · Dec 10, 2023 · 3aa686f · 3aa686f
1 parent a270f61
commit 3aa686f
Show file tree

Hide file tree

Showing 12 changed files with 859 additions and 3 deletions.
diff --git a/target/linux/mediatek/base-files/lib/preinit/05_set_preinit_iface b/target/linux/mediatek/base-files/lib/preinit/05_set_preinit_iface
@@ -1,5 +1,10 @@
 set_preinit_iface() {
 	case $(board_name) in
+	smartrg,sdg-8622|\
+	smartrg,sdg-8632)
+		ip link set lan up
+		ifname=lan
+		;;
 	glinet,gl-mt3000)
 		ip link set eth1 up
 		ifname=eth1

diff --git a/target/linux/mediatek/dts/mt7986a-smartrg-SDG-8612.dts b/target/linux/mediatek/dts/mt7986a-smartrg-SDG-8612.dts
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 SmartRG Inc.
+ * Author: Chad Monroe <[email protected]>
+ */
+
+#include "mt7986a-smartrg-bonanza-peak.dtsi"
+
+/ {
+	model = "SmartRG SDG-8612";
+	compatible = "smartrg,sdg-8612", "mediatek,mt7986a";
+};
+
+&gmac0 {
+	fixed-link {
+		speed = <2500>;
+		full-duplex;
+		pause;
+	};
+};
+
+&gmac1 {
+	phy-handle = <&phy6>;
+};
+
+&mdio {
+	switch: switch@1f {
+		compatible = "mediatek,mt7531";
+		reg = <31>;
+		reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@1 {
+				reg = <1>;
+				label = "lan3";
+			};
+
+			port@2 {
+				reg = <2>;
+				label = "lan2";
+			};
+
+			port@3 {
+				reg = <3>;
+				label = "lan1";
+			};
+
+			port5: port@5 {
+				reg = <5>;
+				label = "lan4";
+
+				phy-mode = "2500base-x";
+				phy-handle = <&phy5>;
+			};
+
+			port@6 {
+				reg = <6>;
+				ethernet = <&gmac0>;
+				phy-mode = "2500base-x";
+
+				fixed-link {
+					speed = <2500>;
+					full-duplex;
+					pause;
+				};
+			};
+		};
+	};
+};
+
+&wifi {
+	ieee80211-freq-limit = <2400000 2500000>, <5170000 5835000>;
+};
diff --git a/target/linux/mediatek/dts/mt7986a-smartrg-SDG-8614.dts b/target/linux/mediatek/dts/mt7986a-smartrg-SDG-8614.dts
@@ -0,0 +1,124 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 SmartRG Inc.
+ * Author: Chad Monroe <[email protected]>
+ */
+
+#include "mt7986a-smartrg-bonanza-peak.dtsi"
+
+/ {
+	model = "SmartRG SDG-8614";
+	compatible = "smartrg,sdg-8614", "mediatek,mt7986a";
+
+	/* SFP1 cage (WAN) */
+	i2c_sfp1: i2c-gpio-0 {
+		compatible = "i2c-gpio";
+		sda-gpios = <&pio 62 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+		scl-gpios = <&pio 63 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+		i2c-gpio,delay-us = <2>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	sfp1: sfp1 {
+		compatible = "sff,sfp";
+		i2c-bus = <&i2c_sfp1>;
+		los-gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
+		mod-def0-gpios = <&pio 65 GPIO_ACTIVE_LOW>;
+		rate-select0-gpios = <&pio 9 GPIO_ACTIVE_HIGH>;
+		rate-select1-gpios = <&pio 28 GPIO_ACTIVE_HIGH>;
+		tx-disable-gpios = <&pio 64 GPIO_ACTIVE_HIGH>;
+		tx-fault-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
+		maximum-power-milliwatt = <3000>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		sfp_red {
+			color = <LED_COLOR_ID_RED>;
+			function = "sfp";
+			function-enumerator = <1>;
+			gpios = <&pio 16 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		sfp_green {
+			color = <LED_COLOR_ID_GREEN>;
+			function = "sfp";
+			function-enumerator = <0>;
+			gpios = <&pio 19 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+	};
+};
+
+&mux_sel {
+	output-low;
+	/delete-node/ output-high;
+};
+
+&gmac0 {
+	fixed-link {
+		speed = <2500>;
+		full-duplex;
+		pause;
+	};
+};
+
+&gmac1 {
+	sfp = <&sfp1>;
+	managed = "in-band-status";
+};
+
+&mdio {
+	switch: switch@1f {
+		compatible = "mediatek,mt7531";
+		reg = <31>;
+		reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@1 {
+				reg = <1>;
+				label = "lan3";
+			};
+
+			port@2 {
+				reg = <2>;
+				label = "lan2";
+			};
+
+			port@3 {
+				reg = <3>;
+				label = "lan1";
+			};
+
+			port5: port@5 {
+				reg = <5>;
+				label = "lan4";
+
+				phy-mode = "2500base-x";
+				phy-handle = <&phy5>;
+			};
+
+			port@6 {
+				reg = <6>;
+				ethernet = <&gmac0>;
+				phy-mode = "2500base-x";
+
+				fixed-link {
+					speed = <2500>;
+					full-duplex;
+					pause;
+				};
+			};
+		};
+	};
+};
+
+&wifi {
+	ieee80211-freq-limit = <2400000 2500000>, <5170000 5835000>;
+};
diff --git a/target/linux/mediatek/dts/mt7986a-smartrg-SDG-8622.dts b/target/linux/mediatek/dts/mt7986a-smartrg-SDG-8622.dts
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 SmartRG Inc.
+ * Author: Chad Monroe <[email protected]>
+ */
+
+#include "mt7986a-smartrg-bonanza-peak.dtsi"
+
+/ {
+	model = "SmartRG SDG-8622";
+	compatible = "smartrg,sdg-8622", "mediatek,mt7986a";
+};
+
+&gmac0 {
+	phy-handle = <&phy5>;
+
+	label = "lan";
+};
+
+&gmac1 {
+	phy-handle = <&phy6>;
+};
+
+&pcie {
+	status = "okay";
+};
+
+&pcie_phy {
+	status = "okay";
+};
+
+&radio0 {
+	ieee80211-freq-limit = <5170000 5330000>;
+};
+
+&wifi {
+	ieee80211-freq-limit = <2400000 2500000>, <5490000 5835000>;
+};
diff --git a/target/linux/mediatek/dts/mt7986a-smartrg-SDG-8632.dts b/target/linux/mediatek/dts/mt7986a-smartrg-SDG-8632.dts
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 SmartRG Inc.
+ * Author: Chad Monroe <[email protected]>
+ */
+
+#include "mt7986a-smartrg-bonanza-peak.dtsi"
+
+/ {
+	model = "SmartRG SDG-8632";
+	compatible = "smartrg,sdg-8632", "mediatek,mt7986a";
+};
+
+&gmac0 {
+	phy-handle = <&phy5>;
+
+	label = "lan";
+};
+
+&gmac1 {
+	phy-handle = <&phy6>;
+};
+
+&pcie {
+	status = "okay";
+};
+
+&pcie_phy {
+	status = "okay";
+};
+
+&radio0 {
+	ieee80211-freq-limit = <5170000 5835000>;
+};
+
+&wifi {
+	ieee80211-freq-limit = <2400000 2500000>, <5945000 7125000>;
+};