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[RISC-V] Code clean-up to debug start-up
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@cyring
cyring committed Feb 23, 2025
1 parent d281660 commit 92c5e0f
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Showing 7 changed files with 204 additions and 3,772 deletions.
74 changes: 48 additions & 26 deletions riscv64/bitasm.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -85,17 +85,18 @@ __asm__ volatile \
)

#define RDTSC64(_mem64) \
__asm__ volatile \
/*TODO __asm__ volatile \
( \
"csrr %0 , mcycle" \
: "=r" (_mem64) \
: \
: "cc", "memory" \
)
)*/ \
_mem64 = 0;

#define ASM_RDTSC(_reg) \
"# Read variant TSC." "\n\t" \
"csrr " #_reg ", mcycle" "\n\t"
"# Read variant TSC." /*TODO "\n\t" \
"csrr " #_reg ", mcycle" "\n\t"*/

#define ASM_CODE_RDPMC(_ctr, _reg) \
"# Read PMU counter." "\n\t" \
Expand Down Expand Up @@ -163,9 +164,9 @@ ASM_RDTSC_PMCx1(x14, x15, ASM_RDTSC, mem_tsc, __VA_ARGS__)

#define _BITSET_GPR(_lock, _base, _offset) \
({ \
volatile unsigned char _ret; \
/* volatile unsigned char _ret; \
\
/* __asm__ volatile \
__asm__ volatile \
( \
"mov x12, #1" "\n\t" \
"lsl x12, x12, %[offset]" "\n\t" \
Expand All @@ -177,14 +178,17 @@ ASM_RDTSC_PMCx1(x14, x15, ASM_RDTSC, mem_tsc, __VA_ARGS__)
[offset] "r" (_offset) \
_BITSET_CLOBBERS_##_lock \
);*/ \
const __typeof__(_base) _shl = 1LLU << _offset; \
const unsigned char _ret = ((_base) & (_shl)) != 0; \
_base = (_base) | (_shl); \
_ret; \
})

#define _BITSET_IMM(_lock, _base, _imm6) \
({ \
volatile unsigned char _ret; \
/* volatile unsigned char _ret; \
\
/* __asm__ volatile \
__asm__ volatile \
( \
"mov x12, #1" "\n\t" \
"lsl x12, x12, %[imm6]" "\n\t" \
Expand All @@ -196,6 +200,9 @@ ASM_RDTSC_PMCx1(x14, x15, ASM_RDTSC, mem_tsc, __VA_ARGS__)
[imm6] "i" (_imm6) \
_BITSET_CLOBBERS_##_lock \
);*/ \
const __typeof__(_base) _shl = 1LLU << _imm6; \
const unsigned char _ret = ((_base) & (_shl)) != 0; \
_base = (_base) | (_shl); \
_ret; \
})

Expand Down Expand Up @@ -228,9 +235,9 @@ ASM_RDTSC_PMCx1(x14, x15, ASM_RDTSC, mem_tsc, __VA_ARGS__)

#define _BITCLR_GPR(_lock, _base, _offset) \
({ \
volatile unsigned char _ret; \
/* volatile unsigned char _ret; \
\
/* __asm__ volatile \
__asm__ volatile \
( \
"mov x12, #1" "\n\t" \
"lsl x12, x12, %[offset]" "\n\t" \
Expand All @@ -242,14 +249,17 @@ ASM_RDTSC_PMCx1(x14, x15, ASM_RDTSC, mem_tsc, __VA_ARGS__)
[offset] "r" (_offset) \
_BITCLR_CLOBBERS_##_lock \
);*/ \
const __typeof__(_base) _shl = 1LLU << _offset; \
const unsigned char _ret = ((_base) & (_shl)) != 0; \
_base = (_base) & ~(_shl); \
_ret; \
})

#define _BITCLR_IMM(_lock, _base, _imm6) \
({ \
volatile unsigned char _ret; \
/* volatile unsigned char _ret; \
\
/* __asm__ volatile \
__asm__ volatile \
( \
"mov x12, #1" "\n\t" \
"lsl x12, x12, %[imm6]" "\n\t" \
Expand All @@ -261,6 +271,9 @@ ASM_RDTSC_PMCx1(x14, x15, ASM_RDTSC, mem_tsc, __VA_ARGS__)
[imm6] "i" (_imm6) \
_BITCLR_CLOBBERS_##_lock \
);*/ \
const __typeof__(_base) _shl = 1LLU << _imm6; \
const unsigned char _ret = ((_base) & (_shl)) != 0; \
_base = (_base) & ~(_shl); \
_ret; \
})

Expand Down Expand Up @@ -292,9 +305,9 @@ ASM_RDTSC_PMCx1(x14, x15, ASM_RDTSC, mem_tsc, __VA_ARGS__)

#define _BIT_TEST_GPR(_lock, _base, _offset) \
({ \
volatile unsigned char _ret; \
/* volatile unsigned char _ret; \
\
/* __asm__ volatile \
__asm__ volatile \
( \
"mov x12, #1" "\n\t" \
"lsl x12, x12, %[offset]" "\n\t" \
Expand All @@ -306,14 +319,15 @@ ASM_RDTSC_PMCx1(x14, x15, ASM_RDTSC, mem_tsc, __VA_ARGS__)
[offset] "r" (_offset) \
_BIT_TEST_CLOBBERS_##_lock \
);*/ \
const unsigned char _ret = ((_base) & (1LLU << _offset)) != 0; \
_ret; \
})

#define _BIT_TEST_IMM(_lock, _base, _imm6) \
({ \
volatile unsigned char _ret; \
/* volatile unsigned char _ret; \
\
/* __asm__ volatile \
__asm__ volatile \
( \
"mov x12, #1" "\n\t" \
"lsl x12, x12, %[imm6]" "\n\t" \
Expand All @@ -325,6 +339,7 @@ ASM_RDTSC_PMCx1(x14, x15, ASM_RDTSC, mem_tsc, __VA_ARGS__)
[imm6] "i" (_imm6) \
_BIT_TEST_CLOBBERS_##_lock \
);*/ \
const unsigned char _ret = ((_base) & (1LLU << _imm6)) != 0; \
_ret; \
})

Expand All @@ -351,9 +366,9 @@ ASM_RDTSC_PMCx1(x14, x15, ASM_RDTSC, mem_tsc, __VA_ARGS__)

#define _BITWISEAND(_lock, _opl, _opr) \
({ \
volatile Bit64 _dest __attribute__ ((aligned (8))); \
/* volatile Bit64 _dest __attribute__ ((aligned (8))); \
\
/* __asm__ volatile \
__asm__ volatile \
( \
_BITWISEAND_PRE_INST_##_lock \
"and x10, x11, %[opr]" "\n\t" \
Expand All @@ -364,6 +379,7 @@ ASM_RDTSC_PMCx1(x14, x15, ASM_RDTSC, mem_tsc, __VA_ARGS__)
[opr] "Lr" (_opr) \
_BITWISEAND_CLOBBERS_##_lock \
);*/ \
const Bit64 _dest __attribute__ ((aligned (8)))=(_opl) & (_opr);\
_dest; \
})

Expand All @@ -390,9 +406,9 @@ ASM_RDTSC_PMCx1(x14, x15, ASM_RDTSC, mem_tsc, __VA_ARGS__)

#define _BITWISEOR(_lock, _opl, _opr) \
({ \
volatile Bit64 _dest __attribute__ ((aligned (8))); \
/* volatile Bit64 _dest __attribute__ ((aligned (8))); \
\
/* __asm__ volatile \
__asm__ volatile \
( \
_BITWISEOR_PRE_INST_##_lock \
"orr x10, x11, %[opr]" "\n\t" \
Expand All @@ -403,6 +419,7 @@ ASM_RDTSC_PMCx1(x14, x15, ASM_RDTSC, mem_tsc, __VA_ARGS__)
[opr] "Lr" (_opr) \
_BITWISEOR_CLOBBERS_##_lock \
);*/ \
const Bit64 _dest __attribute__ ((aligned (8)))=(_opl) | (_opr);\
_dest; \
})

Expand All @@ -429,9 +446,9 @@ ASM_RDTSC_PMCx1(x14, x15, ASM_RDTSC, mem_tsc, __VA_ARGS__)

#define _BITWISEXOR(_lock, _opl, _opr) \
({ \
volatile Bit64 _dest __attribute__ ((aligned (8))); \
/* volatile Bit64 _dest __attribute__ ((aligned (8))); \
\
/* __asm__ volatile \
__asm__ volatile \
( \
_BITWISEXOR_PRE_INST_##_lock \
"eor x10, x11, %[opr]" "\n\t" \
Expand All @@ -442,6 +459,7 @@ ASM_RDTSC_PMCx1(x14, x15, ASM_RDTSC, mem_tsc, __VA_ARGS__)
[opr] "Lr" (_opr) \
_BITWISEXOR_CLOBBERS_##_lock \
);*/ \
const Bit64 _dest __attribute__ ((aligned (8)))=(_opl) ^ (_opr);\
_dest; \
})

Expand Down Expand Up @@ -530,6 +548,7 @@ ASM_RDTSC_PMCx1(x14, x15, ASM_RDTSC, mem_tsc, __VA_ARGS__)
[src] "r" (_src) \
_BITSTOR_CLOBBERS_##_lock \
);*/ \
_dest = _src; \
})

#define BITSTOR(_lock, _dest, _src) \
Expand Down Expand Up @@ -615,6 +634,7 @@ ASM_RDTSC_PMCx1(x14, x15, ASM_RDTSC, mem_tsc, __VA_ARGS__)
[opr] "Lr" (_opr) \
_BITWISESET_CLOBBERS_##_lock \
);*/ \
_BITSTOR(_lock, _opl, _opr); \
})

#define BITWISESET(_lock, _opl, _opr) \
Expand Down Expand Up @@ -643,14 +663,15 @@ ASM_RDTSC_PMCx1(x14, x15, ASM_RDTSC, mem_tsc, __VA_ARGS__)

#define _BITWISECLR(_lock, _dest) \
({ \
__asm__ volatile \
/* __asm__ volatile \
( \
_BITWISECLR_PRE_INST_##_lock \
_BITWISECLR_POST_INST_##_lock \
: \
: [addr] "r" (&_dest) \
_BITWISECLR_CLOBBERS_##_lock \
); \
);*/ \
_dest = 0; \
})

#define BITWISECLR(_lock, _dest) \
Expand Down Expand Up @@ -738,9 +759,9 @@ ASM_RDTSC_PMCx1(x14, x15, ASM_RDTSC, mem_tsc, __VA_ARGS__)

#define _BITCMP(_lock, _opl, _opr) \
({ \
volatile unsigned char _ret; \
/* volatile unsigned char _ret; \
\
/* __asm__ volatile \
__asm__ volatile \
( \
_BITCMP_PRE_INST_##_lock \
"cmp x11, %[opr]" "\n\t" \
Expand All @@ -752,6 +773,7 @@ ASM_RDTSC_PMCx1(x14, x15, ASM_RDTSC, mem_tsc, __VA_ARGS__)
[opr] "Lr" (_opr) \
_BITCMP_CLOBBERS_##_lock \
);*/ \
const unsigned char _ret = _opl == _opr ? 1 : 0; \
_ret; \
})

Expand Down
17 changes: 0 additions & 17 deletions riscv64/corefreq-api.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -200,14 +200,6 @@ typedef struct

struct {
Bit64 FLAGS __attribute__ ((aligned (8)));
Bit64 HCR __attribute__ ((aligned (8)));
Bit64 SCTLR __attribute__ ((aligned (8)));
Bit64 SCTLR2 __attribute__ ((aligned (8)));
Bit64 EL __attribute__ ((aligned (8)));
Bit64 FPSR __attribute__ ((aligned (8)));
Bit64 FPCR __attribute__ ((aligned (8)));
Bit64 SVCR __attribute__ ((aligned (8)));
Bit64 CPACR __attribute__ ((aligned (8)));
} SystemRegister;

unsigned int Bind;
Expand Down Expand Up @@ -331,9 +323,6 @@ typedef struct
signed int ArchID;

struct {
CLUSTERCFR ClusterCfg;
CLUSTERIDR ClusterRev;

unsigned int Boost[UNCORE_BOOST(SIZE)];
BUS_REGISTERS Bus;
MC_REGISTERS MC[MC_MAX_CTRL];
Expand Down Expand Up @@ -397,12 +386,6 @@ typedef struct

BitCC HWP __attribute__ ((aligned (16)));
BitCC VM __attribute__ ((aligned (16)));
BitCC CLRBHB __attribute__ ((aligned (16)));
BitCC CSV2_1 __attribute__ ((aligned (16)));
BitCC CSV2_2 __attribute__ ((aligned (16)));
BitCC CSV2_3 __attribute__ ((aligned (16)));
BitCC CSV3 __attribute__ ((aligned (16)));
BitCC SSBS __attribute__ ((aligned (16)));
struct {
Bit64 Signal __attribute__ ((aligned (8)));
} OS;
Expand Down
40 changes: 13 additions & 27 deletions riscv64/corefreqd.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -39,7 +39,7 @@
sysconf(_SC_PAGESIZE) > 0 ? sysconf(_SC_PAGESIZE) : 4096 \
)

/* AArch64 LDAXP/STLXP alignment, 128-Byte Blocks of Memory */
/* Architecture alignment is at most 128-Byte Blocks of Memory */
static BitCC roomSeed __attribute__ ((aligned (16))) = InitCC(0x0);
static BitCC roomCore __attribute__ ((aligned (16))) = InitCC(0x0);
static BitCC roomClear __attribute__ ((aligned (16))) = InitCC(0x0);
Expand Down Expand Up @@ -687,7 +687,7 @@ void Technology_Update( RO(SHM_STRUCT) *RO(Shm),
void Mitigation_Stage( RO(SHM_STRUCT) *RO(Shm),
RO(PROC) *RO(Proc), RW(PROC) *RW(Proc) )
{
const unsigned short
/* const unsigned short
CLRBHB = BITWISEAND_CC( LOCKLESS,
RW(Proc)->CLRBHB,
RO(Proc)->SPEC_CTRL_Mask) != 0,
Expand All @@ -711,6 +711,14 @@ void Mitigation_Stage( RO(SHM_STRUCT) *RO(Shm),
SSBS = BITCMP_CC( LOCKLESS,
RW(Proc)->SSBS,
RO(Proc)->SPEC_CTRL_Mask );
*/
const unsigned short
CLRBHB = 0,
CSV2_1 = 0,
CSV2_2 = 0,
CSV2_3 = 0,
CSV3 = 0,
SSBS = 0;

RO(Shm)->Proc.Mechanisms.CLRBHB = CLRBHB ? 0b11 : 0b00;

Expand Down Expand Up @@ -755,8 +763,10 @@ void Uncore_Update( RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc),
RO(Shm)->Uncore.CtrlCount = RO(Proc)->Uncore.CtrlCount;
/* Decode the Memory Controller for each found vendor:device */
Chipset[IC_CHIPSET] = RO(Proc)->Features.Info.Vendor.ID;
/*TODO
RO(Shm)->Uncore.ChipID = RO(Proc)->Uncore.ClusterRev.Revision
| (RO(Proc)->Uncore.ClusterRev.Variant << 4);
*/
RO(Shm)->Uncore.Chipset.ArchID = IC_CHIPSET;
/* Copy the chipset codename. */
StrCopy(RO(Shm)->Uncore.Chipset.CodeName,
Expand Down Expand Up @@ -860,30 +870,6 @@ void SystemRegisters( RO(SHM_STRUCT) *RO(Shm), RO(CORE) **RO(Core),
RO(Shm)->Cpu[cpu].SystemRegister.FLAGS = \
RO(Core, AT(cpu))->SystemRegister.FLAGS;

RO(Shm)->Cpu[cpu].SystemRegister.HCR = \
RO(Core, AT(cpu))->SystemRegister.HCR;

RO(Shm)->Cpu[cpu].SystemRegister.SCTLR = \
RO(Core, AT(cpu))->SystemRegister.SCTLR;

RO(Shm)->Cpu[cpu].SystemRegister.SCTLR2 = \
RO(Core, AT(cpu))->SystemRegister.SCTLR2;

RO(Shm)->Cpu[cpu].SystemRegister.EL = \
RO(Core, AT(cpu))->SystemRegister.EL;

RO(Shm)->Cpu[cpu].SystemRegister.FPSR = \
RO(Core, AT(cpu))->SystemRegister.FPSR;

RO(Shm)->Cpu[cpu].SystemRegister.FPCR = \
RO(Core, AT(cpu))->SystemRegister.FPCR;

RO(Shm)->Cpu[cpu].SystemRegister.SVCR = \
RO(Core, AT(cpu))->SystemRegister.SVCR;

RO(Shm)->Cpu[cpu].SystemRegister.CPACR = \
RO(Core, AT(cpu))->SystemRegister.CPACR;

RO(Shm)->Cpu[cpu].Query.SCTLRX = RO(Core, AT(cpu))->Query.SCTLRX;
}

Expand Down Expand Up @@ -1231,7 +1217,7 @@ void SysGate_Toggle(REF *Ref, unsigned int state)
/* Start SysGate */
BITSET(LOCKLESS, Ref->RO(Shm)->SysGate.Operation, 0);
/* Notify */
BITWISESET(LOCKLESS, PendingSync,BIT_MASK_NTFY);
BITWISESET(LOCKLESS, PendingSync, BIT_MASK_NTFY);
}
}
}
Expand Down
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