signed dword float to and from conversions fcvt.l.s, fcvt.s.l, fcvt.l.d, fcvt.d.l perform unsigned conversions instead

[lenawanel]

see for example in

rvemu/src/cpu.rs

Line 3022 in f55eb5b

self.xregs.write(rd, self.fregs.read(rs1).round() as u64);

in the spec they are described as for example

[..] FCVT.L.D converts a double-precision floating-point number in floating-point register rs1 to a signed [..] 64-bit integer [..] in integer register rd.