add tests for expected signed dword fload conversion behavior

addressess part of d0iasm#33 (comment)
lenawanel · May 29, 2024 · 036cb16 · 036cb16
1 parent f55eb5b
commit 036cb16
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Showing 2 changed files with 64 additions and 4 deletions.
diff --git a/tests/rv32d.rs b/tests/rv32d.rs
@@ -380,7 +380,7 @@ fn fcvtdw_rd_rs1_rs2() {
     emu.cpu.xregs.write(31, -4 as i64 as u64);
 
     let data = vec![
-        0xd3, 0x8f, 0x0f, 0xd2, // fcvt.d.w x31, f31 (rm: 000)
+        0xd3, 0x8f, 0x0f, 0xd2, // fcvt.d.w f31, x31 (rm: 000)
     ];
     let expected_xregs = helper::create_xregs(vec![(31, -4 as i64 as u64)]);
     let expected_fregs = helper::create_fregs(vec![(31, -4.0)]);
@@ -395,14 +395,44 @@ fn fcvtdwu_rd_rs1_rs2() {
     emu.cpu.xregs.write(31, 4);
 
     let data = vec![
-        0xd3, 0x8f, 0x1f, 0xd2, // fcvt.d.wu x31, f31 (rm: 000)
+        0xd3, 0x8f, 0x1f, 0xd2, // fcvt.d.wu f31, x31 (rm: 000)
     ];
     let expected_xregs = helper::create_xregs(vec![(31, 4)]);
     let expected_fregs = helper::create_fregs(vec![(31, 4.0)]);
 
     helper::run(&mut emu, data, &expected_xregs, &expected_fregs);
 }
 
+#[test]
+fn fcvtld_rd_fs1() {
+    let mut emu = Emulator::new();
+
+    emu.cpu.fregs.write(31, -1.0);
+
+    let data = vec![
+        0xd3, 0xff, 0x2f, 0xc2, // fcvt.l.d x31,f31 (rm: 000)
+    ];
+    let expected_xregs = helper::create_xregs(vec![(31, -1i64 as u64)]);
+    let expected_fregs = helper::create_fregs(vec![(31, -1.0)]);
+
+    helper::run(&mut emu, data, &expected_xregs, &expected_fregs);
+}
+
+#[test]
+fn fcvtdl_frd_rs1() {
+    let mut emu = Emulator::new();
+
+    emu.cpu.xregs.write(31, -1i64 as u64);
+
+    let data = vec![
+        0xd3, 0xff, 0x2f, 0xd2, // fcvt.d.l f31,x31 (rm: 000)
+    ];
+    let expected_xregs = helper::create_xregs(vec![(31, -1i64 as u64)]);
+    let expected_fregs = helper::create_fregs(vec![(31, -1.0)]);
+
+    helper::run(&mut emu, data, &expected_xregs, &expected_fregs);
+}
+
 #[test]
 fn fclassd_rd_rs1_rs2() {
     let mut emu = Emulator::new();

diff --git a/tests/rv32f.rs b/tests/rv32f.rs
@@ -356,7 +356,7 @@ fn fcvtsw_rd_rs1_rs2() {
     emu.cpu.xregs.write(31, -4 as i64 as u64);
 
     let data = vec![
-        0xd3, 0x8f, 0x0f, 0xd0, // fcvt.s.w x31, f31 (rm: 000)
+        0xd3, 0x8f, 0x0f, 0xd0, // fcvt.s.w f31, x31 (rm: 000)
     ];
     let expected_xregs = helper::create_xregs(vec![(31, -4 as i64 as u64)]);
     let expected_fregs = helper::create_fregs(vec![(31, -4.0)]);
@@ -371,14 +371,44 @@ fn fcvtswu_rd_rs1_rs2() {
     emu.cpu.xregs.write(31, 4);
 
     let data = vec![
-        0xd3, 0x8f, 0x1f, 0xd0, // fcvt.s.wu x31, f31 (rm: 000)
+        0xd3, 0x8f, 0x1f, 0xd0, // fcvt.s.wu f31, x31 (rm: 000)
     ];
     let expected_xregs = helper::create_xregs(vec![(31, 4)]);
     let expected_fregs = helper::create_fregs(vec![(31, 4.0)]);
 
     helper::run(&mut emu, data, &expected_xregs, &expected_fregs);
 }
 
+#[test]
+fn fcvtls_rd_fs1() {
+    let mut emu = Emulator::new();
+
+    emu.cpu.fregs.write(31, -1.0);
+
+    let data = vec![
+        0xd3, 0xff, 0x2f, 0xc0, // fcvt.l.s x31,f31 (rm: 000)
+    ];
+    let expected_xregs = helper::create_xregs(vec![(31, -1i64 as u64)]);
+    let expected_fregs = helper::create_fregs(vec![(31, -1.0)]);
+
+    helper::run(&mut emu, data, &expected_xregs, &expected_fregs);
+}
+
+#[test]
+fn fcvtsl_frd_rs1() {
+    let mut emu = Emulator::new();
+
+    emu.cpu.xregs.write(31, -1i64 as u64);
+
+    let data = vec![
+        0xd3, 0xff, 0x2f, 0xd0, // fcvt.s.l f31,x31 (rm: 000)
+    ];
+    let expected_xregs = helper::create_xregs(vec![(31, -1i64 as u64)]);
+    let expected_fregs = helper::create_fregs(vec![(31, -1.0)]);
+
+    helper::run(&mut emu, data, &expected_xregs, &expected_fregs);
+}
+
 #[test]
 fn fmvxw_rd_rs1_rs2() {
     let mut emu = Emulator::new();