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Fcvt fix #34

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Fcvt fix #34

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036cb16
add tests for expected signed dword fload conversion behavior
lenawanel May 29, 2024
786534d
fix the conversion issue
lenawanel May 29, 2024
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10 changes: 6 additions & 4 deletions src/cpu.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -2979,7 +2979,7 @@ impl Cpu {
self.debug(inst, "fcvt.l.s");

self.xregs
.write(rd, (self.fregs.read(rs1) as f32).round() as u64);
.write(rd, (self.fregs.read(rs1) as f32).round() as i64 as u64);
}
0x3 => {
// fcvt.lu.s
Expand Down Expand Up @@ -3019,7 +3019,8 @@ impl Cpu {
inst_count!(self, "fcvt.l.d");
self.debug(inst, "fcvt.l.d");

self.xregs.write(rd, self.fregs.read(rs1).round() as u64);
self.xregs
.write(rd, self.fregs.read(rs1).round() as i64 as u64);
}
0x3 => {
// fcvt.lu.d
Expand Down Expand Up @@ -3056,7 +3057,8 @@ impl Cpu {
inst_count!(self, "fcvt.s.l");
self.debug(inst, "fcvt.s.l");

self.fregs.write(rd, (self.xregs.read(rs1) as f32) as f64);
self.fregs
.write(rd, (self.xregs.read(rs1) as i64 as f32) as f64);
}
0x3 => {
// fcvt.s.lu
Expand Down Expand Up @@ -3092,7 +3094,7 @@ impl Cpu {
inst_count!(self, "fcvt.d.l");
self.debug(inst, "fcvt.d.l");

self.fregs.write(rd, self.xregs.read(rs1) as f64);
self.fregs.write(rd, self.xregs.read(rs1) as i64 as f64);
}
0x3 => {
// fcvt.d.lu
Expand Down
34 changes: 32 additions & 2 deletions tests/rv32d.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -380,7 +380,7 @@ fn fcvtdw_rd_rs1_rs2() {
emu.cpu.xregs.write(31, -4 as i64 as u64);

let data = vec![
0xd3, 0x8f, 0x0f, 0xd2, // fcvt.d.w x31, f31 (rm: 000)
0xd3, 0x8f, 0x0f, 0xd2, // fcvt.d.w f31, x31 (rm: 000)
];
let expected_xregs = helper::create_xregs(vec![(31, -4 as i64 as u64)]);
let expected_fregs = helper::create_fregs(vec![(31, -4.0)]);
Expand All @@ -395,14 +395,44 @@ fn fcvtdwu_rd_rs1_rs2() {
emu.cpu.xregs.write(31, 4);

let data = vec![
0xd3, 0x8f, 0x1f, 0xd2, // fcvt.d.wu x31, f31 (rm: 000)
0xd3, 0x8f, 0x1f, 0xd2, // fcvt.d.wu f31, x31 (rm: 000)
];
let expected_xregs = helper::create_xregs(vec![(31, 4)]);
let expected_fregs = helper::create_fregs(vec![(31, 4.0)]);

helper::run(&mut emu, data, &expected_xregs, &expected_fregs);
}

#[test]
fn fcvtld_rd_fs1() {
let mut emu = Emulator::new();

emu.cpu.fregs.write(31, -1.0);

let data = vec![
0xd3, 0xff, 0x2f, 0xc2, // fcvt.l.d x31,f31 (rm: 000)
];
let expected_xregs = helper::create_xregs(vec![(31, -1i64 as u64)]);
let expected_fregs = helper::create_fregs(vec![(31, -1.0)]);

helper::run(&mut emu, data, &expected_xregs, &expected_fregs);
}

#[test]
fn fcvtdl_frd_rs1() {
let mut emu = Emulator::new();

emu.cpu.xregs.write(31, -1i64 as u64);

let data = vec![
0xd3, 0xff, 0x2f, 0xd2, // fcvt.d.l f31,x31 (rm: 000)
];
let expected_xregs = helper::create_xregs(vec![(31, -1i64 as u64)]);
let expected_fregs = helper::create_fregs(vec![(31, -1.0)]);

helper::run(&mut emu, data, &expected_xregs, &expected_fregs);
}

#[test]
fn fclassd_rd_rs1_rs2() {
let mut emu = Emulator::new();
Expand Down
34 changes: 32 additions & 2 deletions tests/rv32f.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -356,7 +356,7 @@ fn fcvtsw_rd_rs1_rs2() {
emu.cpu.xregs.write(31, -4 as i64 as u64);

let data = vec![
0xd3, 0x8f, 0x0f, 0xd0, // fcvt.s.w x31, f31 (rm: 000)
0xd3, 0x8f, 0x0f, 0xd0, // fcvt.s.w f31, x31 (rm: 000)
];
let expected_xregs = helper::create_xregs(vec![(31, -4 as i64 as u64)]);
let expected_fregs = helper::create_fregs(vec![(31, -4.0)]);
Expand All @@ -371,14 +371,44 @@ fn fcvtswu_rd_rs1_rs2() {
emu.cpu.xregs.write(31, 4);

let data = vec![
0xd3, 0x8f, 0x1f, 0xd0, // fcvt.s.wu x31, f31 (rm: 000)
0xd3, 0x8f, 0x1f, 0xd0, // fcvt.s.wu f31, x31 (rm: 000)
];
let expected_xregs = helper::create_xregs(vec![(31, 4)]);
let expected_fregs = helper::create_fregs(vec![(31, 4.0)]);

helper::run(&mut emu, data, &expected_xregs, &expected_fregs);
}

#[test]
fn fcvtls_rd_fs1() {
let mut emu = Emulator::new();

emu.cpu.fregs.write(31, -1.0);

let data = vec![
0xd3, 0xff, 0x2f, 0xc0, // fcvt.l.s x31,f31 (rm: 000)
];
let expected_xregs = helper::create_xregs(vec![(31, -1i64 as u64)]);
let expected_fregs = helper::create_fregs(vec![(31, -1.0)]);

helper::run(&mut emu, data, &expected_xregs, &expected_fregs);
}

#[test]
fn fcvtsl_frd_rs1() {
let mut emu = Emulator::new();

emu.cpu.xregs.write(31, -1i64 as u64);

let data = vec![
0xd3, 0xff, 0x2f, 0xd0, // fcvt.s.l f31,x31 (rm: 000)
];
let expected_xregs = helper::create_xregs(vec![(31, -1i64 as u64)]);
let expected_fregs = helper::create_fregs(vec![(31, -1.0)]);

helper::run(&mut emu, data, &expected_xregs, &expected_fregs);
}

#[test]
fn fmvxw_rd_rs1_rs2() {
let mut emu = Emulator::new();
Expand Down