Merge pull request #81 from nsauzede/f-ns-mister

Add new board DE10-Nano w/ Intel Cyclone V (MiSTer)

boards/de10nano_cyclonev_mister/README.md

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+# DE10-Nano board (Terasic) / MiSTer
+
+## General information
+The DE10-Nano board is a robust development board based on Intel/Altera Cyclone V family of FPGAs.\
+It has an Intel Cyclone® V SE 5CSEBA6U23I7 device (110K LEs) and also includes the following peripherals:
+* 64Mbit Flash Memory (EPCS64)
+* 800MHz Dual-core ARM Cortex-A9 processor (HPS)
+* 1GB DDR3 SDRAM (32-bit data bus, HPS)
+* 1 Gigabit Ethernet PHY with RJ45 connector (HPS)
+* USB-Blaster II onboard for programming; JTAG Mode
+* HDMI TX, compatible with DVI 1.0 and HDCP v1.4
+* 8 LEDs + 2 push-buttons
+* Three 50 MHz clock sources
+* Many headers: 40pins, Arduino R3, JTAG..
+* And more..
+
+NOTE: This Darkriscv port targets/integrates the MiSTer framework around the DE10-Nano.
+Some of their files are licensed under GPL v2+ (See LICENSE).
+
+For more detailed information, see here:\
+https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=167&No=1046
+
+https://github.com/MiSTer-devel/Wiki_MiSTer/wiki
+
+The DarkRISCV/darksoc builds out-of-the box using Quartus command-line,
+taking about ~10% of the on-chip logic for the SoC demo (including Mister resources).
+- It uses an altera pll QIP to transform 50MHz into several freqs for MiSTer (TODO: maybe integrate it into darkpll),
+- and a simplified darkram based on altsyncram to properly infer BRAM (TODO: maybe integrate it into darkram).
+
+## Instructions
+Install Quartus with Cyclone V support, `srecord`, `awk`, `xxd`.\
+Read/apply the Terasic docs to enable the cyclone V support (eg: udev rules, ftdi driver etc..)\
+Ensure that `QUARTUS` macro defined in `boards/de10nano_cyclonev_mister/darksocv.mk` points to your Quartus install, then, from darkriscv root directory:\
+Build the bitstream:
+```
+make all BOARD=de10nano_cyclonev_mister
+```
+To program the device, you must transfer the resulting `boards/de10nano_cyclonev_mister/output_files/darkriscv_de10nano.rbf` to your device
+and program it using the MiSTer menu.
+One way to do this is to copy the RBF to your MiSTer via Ethernet, or using an USB stick.
+
+Finally to connect to the serial port, first ensure that the VT52 core SerialPort=ConsolePort;
+then you can use `screen` on the MiSTer via ssh:
+```
+TERM=linux ssh -t root@<MiSTer_IP_Address> screen /dev/ttyS1 115200
+```
+and you should see DarkRISCV booting up:
+```
+...
+board: de10nano cyclonev mister (id=20)
+...
+36253> led aa55
+led = aa55
+1>
+```
+You should see DEBUG on upper 4 leds, and LED on the lower ones.
+
+To clean the board-related objects:
+```
+make clean BOARD=de10nano_cyclonev_mister
+```

boards/de10nano_cyclonev_mister/_darkram.v

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+`timescale 1ns / 1ps
+`include "../../rtl/config.vh"
+
+module darkram #(parameter INIT_FILE = "../memory_init.mif")
+(
+    input           CLK,    // Clock
+    input           RES,    // Reset
+    input           HLT,    // Halt
+
+    input           IDREQ,  // Instruction fetch request
+    input  [31:0]   IADDR,  // Instruction address
+    output [31:0]   IDATA,  // Instruction data output
+    output          IDACK,  // Instruction acknowledge
+
+    input           XDREQ,  // Data request
+    input           XRD,    // Read enable
+    input           XWR,    // Write enable
+    input  [3:0]    XBE,    // Byte enable
+    input  [31:0]   XADDR,  // Data address
+    input  [31:0]   XATAI,  // Data input
+    output [31:0]   XATAO,  // Data output
+    output          XDACK,  // Data acknowledge
+
+    output [3:0]    DEBUG   // Debug signals
+);
+
+    // Internal signals
+    wire [31:0] ram_q_a, ram_q_b;
+    wire        write_enable;
+
+
+    // Instantiate altsyncram
+    altsyncram #(
+        .operation_mode("BIDIR_DUAL_PORT"),
+        .width_a(32),
+        .widthad_a(13),  // Address width for 4KB RAM
+        .numwords_a(2048),
+        .width_b(32),
+        .widthad_b(13),
+        .numwords_b(2048),
+        .lpm_type("altsyncram"),
+        .ram_block_type("AUTO"),
+        .init_file(INIT_FILE),
+        .outdata_reg_a("UNREGISTERED"),
+        .outdata_reg_b("UNREGISTERED"),
+        .indata_reg_b("CLOCK0"),
+        .address_reg_b("CLOCK0"),
+        .wrcontrol_wraddress_reg_b("CLOCK0"),
+        .byte_size(8),
+        .width_byteena_a(4),
+        .width_byteena_b(4),
+        .byteena_reg_b("CLOCK0")
+    ) ram_inst (
+        .clock0(CLK),
+        .address_a(IADDR[12:2]),
+        .q_a(ram_q_a),
+        .address_b(XADDR[12:2]),
+        .wren_b(write_enable),
+        .byteena_b(XBE),
+        .data_b(XATAI),
+        .q_b(ram_q_b)
+    );
+    assign write_enable = XWR & XDREQ;
+
+    // Assign instruction fetch outputs
+    assign IDATA = ram_q_a;
+    assign IDACK = IDREQ;  // Immediate ACK for simplicity
+
+    // Assign data read/write outputs
+    assign XATAO = ram_q_b;
+    assign XDACK = DTACK==1 ||(XDREQ&&XWR);
+    reg [3:0] DTACK  = 0;
+    always@(posedge CLK) // stage #1.0
+    begin
+        DTACK <= RES ? 0 : DTACK ? DTACK-1 : XDREQ && XRD ? 1 : 0;
+    end
+
+    // Debug outputs (for observability)
+    assign DEBUG = { XDREQ,XRD,XWR,XDACK };
+
+endmodule

boards/de10nano_cyclonev_mister/bin2mif.sh

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+#!/bin/bash
+
+WORD=4
+SRC=memory_init.bin;DST=memory_init.mif
+srec_cat $SRC -binary -byte-swap 4 -o $DST -mif $WORD

boards/de10nano_cyclonev_mister/darkriscv_de10nano.qpf

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+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2018  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
+# Date created = 18:23:56  January 08, 2019
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "18.1"
+DATE = "18:23:56  January 08, 2019"
+
+# Revisions
+
+PROJECT_REVISION = "darkriscv_de10nano"

boards/de10nano_cyclonev_mister/darkriscv_de10nano.qsf

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+# --------------------------------------------------------------------------
+#
+# MiSTer project
+#
+# WARNING WARNING WARNING:
+# Do not add files to project in Quartus IDE! It will mess this file!
+# Add the files manually to files.qip file.
+#
+# --------------------------------------------------------------------------
+
+set_global_assignment -name TOP_LEVEL_ENTITY sys_top
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+
+set_global_assignment -name LAST_QUARTUS_VERSION "17.0.2 Lite Edition"
+
+set_global_assignment -name GENERATE_RBF_FILE ON
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
+set_global_assignment -name SAVE_DISK_SPACE OFF
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
+set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
+set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
+set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
+set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
+set_global_assignment -name ALLOW_POWER_UP_DONT_CARE ON
+set_global_assignment -name QII_AUTO_PACKED_REGISTERS NORMAL
+set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
+set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name MUX_RESTRUCTURE ON
+set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
+set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
+set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
+set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION ON
+set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON
+set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
+set_global_assignment -name ECO_OPTIMIZE_TIMING ON
+set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
+set_global_assignment -name ALM_REGISTER_PACKING_EFFORT MEDIUM
+set_global_assignment -name SEED 1
+
+#set_global_assignment -name VERILOG_MACRO "MISTER_FB=1"
+
+#enable it only if 8bit indexed mode is used in core
+#set_global_assignment -name VERILOG_MACRO "MISTER_FB_PALETTE=1"
+
+#set_global_assignment -name VERILOG_MACRO "MISTER_DUAL_SDRAM=1"
+
+#do not enable DEBUG_NOHDMI in release!
+set_global_assignment -name VERILOG_MACRO "MISTER_DEBUG_NOHDMI=1"
+
+set_global_assignment -name VERILOG_MACRO "DE10NANO_CYCLONEV_MISTER=1"
+
+source sys/sys.tcl
+source sys/sys_analog.tcl
+source files.qip
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

boards/de10nano_cyclonev_mister/darkriscv_de10nano.sdc

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+derive_pll_clocks
+derive_clock_uncertainty
+
+# core specific constraints