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Original file line number | Diff line number | Diff line change |
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const t="/zh-cn/assets/cover-9c53ea5f.png",l="/zh-cn/assets/image1-0a18e154.png",e=[t,l],r={label:"欢迎加入达坦科技硬件设计学习社区",description:"近年来随着Bluespec、Chisel、SpinalHDL、PyMTL等一众新一代HDL的推出,业界逐步感受到新一代HDL在数字芯片设计效率方面的提升。相比Verilog和VHDL,这些新一代HDL在语法表达能力、代码简洁程度、错误检查等方面有不小的提升;相比高阶综合HLS,这些新一代HDL支持RTL级描述能力,在芯片性能的把控方面远超HSL。数字芯片的敏捷设计,其目的就是为了提升硬件设计效率,减少人为错误。无论用哪一种语言进行硬件设计,背后扎实的硬件设计相关知识是必不可少的,特别是体系结构,因为体系结构专门研究CPU设计,而CPU是当今最复杂的数字芯片之一,各种常见的数字芯片设计问题在体系结构领域都能找到对应的参照,诸如流水线、缓存、内存管理、缓存一致性、异常处理等等。",cover:"./cover.png",location:"新加坡",date:"2023-01-12",title:"Welcome to join Datan Technology hardware design learning community"},s=[{label:"学习目的",level:2},{label:"学习内容",level:2},{label:"适合人群",level:2},{label:"学习方式",level:2},{label:"学习规划",level:2},{label:"参与方式",level:2}],o=`<p>近年来随着 Bluespec、Chisel、SpinalHDL、PyMTL 等一众新一代 HDL 的推出,业界逐步感受到新一代 HDL 在数字芯片设计效率方面的提升。相比 Verilog 和 VHDL,这些新一代 HDL 在语法表达能力、代码简洁程度、错误检查等方面有不小的提升;相比高阶综合 HLS,这些新一代 HDL 支持 RTL 级描述能力,在芯片性能的把控方面远超 HSL。数字芯片的敏捷设计,其目的就是为了提升硬件设计效率,减少人为错误。无论用哪一种语言进行硬件设计,背后扎实的硬件设计相关知识是必不可少的,特别是体系结构,因为体系结构专门研究 CPU 设计,而 CPU 是当今最复杂的数字芯片之一,各种常见的数字芯片设计问题在体系结构领域都能找到对应的参照,诸如流水线、缓存、内存管理、缓存一致性、异常处理等等。</p> | ||
const t="/zh-cn/assets/cover-9c53ea5f.png",l="/zh-cn/assets/image1-0a18e154.png",e=[t,l],s={label:"欢迎加入达坦科技硬件设计学习社区",description:"近年来随着Bluespec、Chisel、SpinalHDL、PyMTL等一众新一代HDL的推出,业界逐步感受到新一代HDL在数字芯片设计效率方面的提升。相比Verilog和VHDL,这些新一代HDL在语法表达能力、代码简洁程度、错误检查等方面有不小的提升;相比高阶综合HLS,这些新一代HDL支持RTL级描述能力,在芯片性能的把控方面远超HSL。数字芯片的敏捷设计,其目的就是为了提升硬件设计效率,减少人为错误。无论用哪一种语言进行硬件设计,背后扎实的硬件设计相关知识是必不可少的,特别是体系结构,因为体系结构专门研究CPU设计,而CPU是当今最复杂的数字芯片之一,各种常见的数字芯片设计问题在体系结构领域都能找到对应的参照,诸如流水线、缓存、内存管理、缓存一致性、异常处理等等。",cover:"./cover.png",location:"新加坡",date:"2023-01-12",title:"Welcome to join Datan Technology hardware design learning community"},r=[{label:"学习目的",level:2},{label:"学习内容",level:2},{label:"适合人群",level:2},{label:"学习方式",level:2},{label:"学习规划",level:2},{label:"参与方式",level:2}],o=`<p>近年来随着 Bluespec、Chisel、SpinalHDL、PyMTL 等一众新一代 HDL 的推出,业界逐步感受到新一代 HDL 在数字芯片设计效率方面的提升。相比 Verilog 和 VHDL,这些新一代 HDL 在语法表达能力、代码简洁程度、错误检查等方面有不小的提升;相比高阶综合 HLS,这些新一代 HDL 支持 RTL 级描述能力,在芯片性能的把控方面远超 HSL。数字芯片的敏捷设计,其目的就是为了提升硬件设计效率,减少人为错误。无论用哪一种语言进行硬件设计,背后扎实的硬件设计相关知识是必不可少的,特别是体系结构,因为体系结构专门研究 CPU 设计,而 CPU 是当今最复杂的数字芯片之一,各种常见的数字芯片设计问题在体系结构领域都能找到对应的参照,诸如流水线、缓存、内存管理、缓存一致性、异常处理等等。</p> | ||
<p>虽然国内大专院校计算机科学和电子工程专业都有开设体系结构或组成原理等相关课程,但是在实操环节缺失很多内容,特别是 CPU 里缓存、内存管理、异常处理相关的部分,基本上都不涉及。但是随着数字芯片的规模越来越大,芯片设计的复杂度指数级上升,对数字芯片的设计人员有很高的要求。<strong>当有志从事数字芯片设计的同学从学校走向社会,如何理解数字芯片设计的精髓,提升设计能力,成为能否胜任数字芯片设计工作的关键。</strong></p> | ||
<p>为此,达坦科技在 2023 年始,<strong>发起成立硬件设计学习社区</strong>,诚邀所有对硬件敏捷开发设计感兴趣的同学加入我们的学习社区。这里有志同道合的小伙伴,共同学习目标的互助自学小组,有耐心答疑的助教。我们一起花一个月的时间,系统地学习计算机体系结构相关知识,并且通过动手项目来验证学习的成果。</p> | ||
<h2 id="学习目的">学习目的</h2> | ||
|
@@ -42,4 +42,4 @@ const t="/zh-cn/assets/cover-9c53ea5f.png",l="/zh-cn/assets/image1-0a18e154.png" | |
<li>准备好个人的简历,内容包括但不局限于:学校/专业、过往学术/项目经验</li> | ||
<li>扫码联系小助手报名邮箱<a href="mailto:[email protected]">[email protected]</a>注册学习档案,通过后加入硬件设计学习社区群即参与成功。</li> | ||
</ul> | ||
<p><img src="${l}" alt="图片"></p>`;export{e as assetURLs,o as default,r as metadata,s as toc}; | ||
<p><img src="${l}" alt="图片"></p>`;export{e as assetURLs,o as default,s as metadata,r as toc}; |
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