Skip to content
View deo248's full-sized avatar
0 followers · 2 following

Block or report deo248

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
deo248/README.md

Computer architect, SoC design, FPGA/ASIC hardware developer

Pinned Loading

  1. steveicarus/iverilog steveicarus/iverilog Public

    Icarus Verilog

    C++ 2.8k 522

  2. verilator/verilator verilator/verilator Public

    Verilator open-source SystemVerilog simulator and lint system

    C++ 2.5k 590

  3. vhda/verilog_systemverilog.vim vhda/verilog_systemverilog.vim Public

    Verilog/SystemVerilog Syntax and Omni-completion

    Vim Script 366 89