The Berkeley Out-of-Order Machine (BOOM) is a synthesizable and parameterizable open source RV64GC RISC-V core written in the Chisel hardware construction language. While BOOM is primarily ASIC optimized, it is also usable on FPGAs. We support the FireSim flow to run BOOM at 90+ MHz on FPGAs on Amazon EC2 F1. Created at the University of California, Berkeley in the Berkeley Architecture Research group, its focus is to create a high performance, synthesizable, and parameterizable core for architecture research.
| Feature | BOOM |
|---|---|
| ISA | RISC-V (RV64GC) |
| Synthesizable | √ |
| FPGA | √ |
| Parameterized | √ |
| Floating Point (IEEE 754-2008) | √ |
| Atomic Memory Op Support | √ |
| Caches | √ |
| Virtual Memory | √ |
| Boots Linux | √ |
| Boots Fedora | √ |
| Privileged Arch v1.11 | √ |
| External Debug | √ |
Please check out the BOOM website @ https://boom-core.org for the most up-to-date information. It contains links to the mailing lists, documentation, design spec., publications and more!
Website: (www.boom-core.org)
Mailing List (https://groups.google.com/forum/#!forum/riscv-boom)
This repository is NOT A SELF-RUNNING repository. To instantiate a BOOM core, please use the Chipyard SoC generator.
The current hash of Chipyard that works with this repository is located in the CHIPYARD.hash
file in the top level directory of this repository. This file is mainly used for CI purposes, since
Chipyard should follow the correct version of rocket-chip. For most users, you should be able to
clone Chipyard separately and follow the default Chipyard instructions (without having to use the .hash file).
The RISC-V Privileged ISA, Platform, and Debug specs are still in flux. BOOM will do its best to stay up-to-date with it!
BOOM is a work-in-progress and remains in active development.
Please see CONTRIB_AND_STYLE.md