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Fix for lowering for expressions given as named properties #1217

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Aug 4, 2025
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8 changes: 8 additions & 0 deletions regression/verilog/property/named_property3.desc
Original file line number Diff line number Diff line change
@@ -0,0 +1,8 @@
CORE
named_property3.sv

^EXIT=0$
^SIGNAL=0$
--
^warning: ignoring
--
12 changes: 12 additions & 0 deletions regression/verilog/property/named_property3.sv
Original file line number Diff line number Diff line change
@@ -0,0 +1,12 @@
module main;

wire [31:0] x = 'b10010001;

property with_index;
// the index expression requires lowering
x[7:4] == 'b1001
endproperty

assert property (with_index);

endmodule
5 changes: 4 additions & 1 deletion src/verilog/verilog_synthesis.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -90,8 +90,11 @@ exprt verilog_synthesist::synth_expr_rec(exprt expr, symbol_statet symbol_state)
// substitute
assert(symbol.value.is_not_nil());

// These aren't lowered yet
auto lowered = verilog_lowering(symbol.value);

// recursive call
return synth_expr_rec(symbol.value, symbol_state);
return synth_expr_rec(lowered, symbol_state);
}
else
{
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