Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

SystemVerilog: package scope operator #925

Merged
merged 1 commit into from
Jan 13, 2025
Merged

SystemVerilog: package scope operator #925

merged 1 commit into from
Jan 13, 2025

Conversation

kroening
Copy link
Member

@kroening kroening commented Jan 11, 2025 •
edited
Loading

This adds the SystemVerilog package scope operator ::.

@kroening kroening force-pushed the sv-packages branch 2 times, most recently from bf21558 to 3a3a576 Compare January 13, 2025 00:43
@kroening kroening changed the title SystemVerilog: packages SystemVerilog: package scope operator Jan 13, 2025
@kroening kroening marked this pull request as ready for review January 13, 2025 00:45
@kroening
SystemVerilog: package scope operator
51a824d 
This adds the SystemVerilog package scope operator ::.
@tautschnig tautschnig merged commit 698d536 into main Jan 13, 2025
9 checks passed
@tautschnig tautschnig deleted the sv-packages branch January 13, 2025 10:01
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Reviewers

@tautschnig tautschnig tautschnig approved these changes

Assignees
No one assigned
Labels
Verilog
Projects
None yet
Milestone
No milestone
Development

Successfully merging this pull request may close these issues.
2 participants
@kroening @tautschnig