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Merge pull request #12176 from amaltaro/fix-12121
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Fix T1 site cores ResourceControl logic
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amaltaro authored Dec 2, 2024
2 parents f4f0dc8 + 5b9221e commit 0df84ad
Showing 1 changed file with 2 additions and 2 deletions.
Original file line number Diff line number Diff line change
Expand Up @@ -214,8 +214,8 @@ def checkSlotsChanges(self, infoRC, infoSSB):
for site in set(infoRC).intersection(set(infoSSB)):
if self.tier0Mode and site.startswith('T1_'):
# T1 cores utilization for Tier0
infoSSB[site]['slotsCPU'] *= self.t1SitesCores // 100
infoSSB[site]['slotsIO'] *= self.t1SitesCores // 100
infoSSB[site]['slotsCPU'] = int(infoSSB[site]['slotsCPU'] * self.t1SitesCores / 100)
infoSSB[site]['slotsIO'] = int(infoSSB[site]['slotsIO'] * self.t1SitesCores / 100)
else:
# round very small sites to the bare minimum
infoSSB[site]['slotsCPU'] = max(infoSSB[site]['slotsCPU'], self.minCPUSlots)
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