Change: Slight doc update

README.md

@@ -49,9 +49,10 @@ Features
     - Seamless support of AXI4 vs AXI4-lite
 - CDC support in master & slave interface, to convert an agent clock domain
   from/to the fabric clock domain
-- Round-robin fair-share arbitration
-    - Non-blocking arbitration between requesters
-    - Priority configurable per master interface
+- Round-robin arbitration
+    - Non-blocking arbitration between requesters, with fait-share granting
+    - Priority configurable per master interface, up to 4 different levels,
+      for request and completion stages
 - AXI or AXI4-Lite mode:
     - LITE mode: route all signals described in AXI4-lite specification
     - FULL mode: route all signals described by AXI4 specification
@@ -71,7 +72,7 @@ Features
     - Data width configurable, any width
     - ID width configurable, any width
 - Advanced clock/reset network
-    - Support both asynchronous and synchronous reset schemes
+    - Support both asynchronous and synchronous reset policies
     - Can handle clock domain crossing if needed, the core being fueled by its
       own clock domain
 - Route read/write requests by address decoding. All slave agents are mapped
@@ -80,7 +81,7 @@ Features
   mask used to identified the route to drive back a completion
 - Configurable routing across the infrastructure
     - A master can be restricted to a memory map subset
-    - An acccess to a forbidden area is completed by a DECERR
+    - An access to a forbidden area is completed by a `DECERR`
 - Switching logic IO interfaces can be pipelined to achieve timing closure easier
 - Don't garantee completion ordering when a master targets multiple slaves with the
   same AXI ID (!). A master should use different IDs and reorder the completion by itself
@@ -110,6 +111,9 @@ Core features:
 - Address translation service to connect multiple systems together
 - Timeout support in switching logic
 - Debug interface to steam out events like 4KB crossing or timeout
+- New Checkers:
+    - Check address overlap (start+end vs next slave start address)
+    - ID overlap: mask ID + OR number supported up to next slave ID
 
 Wizard:
 - Number of master and slave agents configurable
@@ -127,9 +131,6 @@ Simulation:
 - Error injection in the core and tesbench
 - Implement statistics in testbench to track misrouting, address distribution,
   master granting, ...
-- New Checkers:
-    - Check address overlap (start+end vs next slave start address)
-    - ID overlap: mask ID + OR number supported up to next slave ID
 
 ## License
 

doc/architecture.md

@@ -82,15 +82,12 @@ the phase regarding the other clocks. The core proposes a CDC stage for each
 interface to convert the clock to the interconnect clock domain. The CDC stage
 is implemented with a [DC-FIFO](https://github.com/dpretet/async_fifo).
 
-The user can also use the same clock for all the interfaces. In this
-configuration, all the agents connected to the core have to use the same clock
-than the interconnect switching logic.
 
 ### Reset
 
 The core fully supports both asynchronous and synchronous reset. The choice
 between these two options depends to the technology targeted. Most of the time,
-asynchronous reset schema is the prefered option. It is STRONGLY ADVICED TO
+asynchronous reset policy is the prefered option. It is STRONGLY ADVICED TO
 NOT MIX THESE TWO RESET TYPES, and choose for instance asynchronous reset only
 for the core and ALL the interfaces. The available resets, named uniformly
 across the interfaces, are:
@@ -112,6 +109,7 @@ Further details can be found in this
 [excellent document](http://www.sunburst-design.com/papers/CummingsSNUG2003Boston_Resets.pdf)
 from the excellent Clifford Cummings.
 
+
 ### Clock Domain Crossing
 
 The core provides a CDC stage for each master or slave interface if needed. The stage is 
@@ -122,6 +120,19 @@ the fabric (same frequency & phase). If an agent uses the same clock than the fa
 agent must also use the same reset to ensure a clean reset sequence.
 
 
+### Boot time
+
+In order to boot properly the interconnect infrastructure, the user must follow the following
+sequence:
+1. Drive low all the reset inputs
+2. Source all the clocks of the active interface
+3. Wait for several clock cycles, for each clock domain, to be sure the whole logic has been reset
+4. Before releasing the resets, be sure all the domains has been completly reset (point 3). Some 
+   clock can be very slower than another domain, be sure to take it in account.
+5. Release the resets
+6. Start to issue request in the core
+
+
 ## AXI4 / AXI4-lite support
 
 The core supports both AXI4 and AXI4-lite protocol by a single parameter setup.
@@ -151,9 +162,15 @@ BUSER and RUSER). These bus fields of the AMBA channels can be activated
 individually, e.g. for address channel only and configured to any width. This
 applies for both AXI4 and AXI4-lite configuration.
 
+The core proposes a top level for [AXI4](../rtl/axicb_crossbar_top.sv), and a 
+top level for [AXI4-lite](../rtl/axicb_crossbar_lite_top.sv). Each supports up 
+to 4 masters and 4 slaves. If the user needs less than 4 agents, it can tied
+to 0 the input signals of an interface, and leave unconnected the outputs.
+
+
 ### Ordering rules
 
-The core supports outstanding requests, and so manages traffic queues.
+The core supports outstanding requests, and so manages traffic queues for each master.
 
 The core doesn't support ID reodering to enhance quality-of-service and so the user
 can be sure the read or write requests will be issued to the master interface(s)
@@ -194,10 +211,6 @@ AXI4-lite supports WSTRB and the core too. It doesn't manipulate this field and
 the user is responsible to drive correctly this field according the
 specification.
 
-AXI4-lite doesn't support `xLAST` signals. The core handles them internally for
-its own purpose and the user doesn't need to take care of them. The user can
-tied them to `0` or `1` or leave them unconnected.
-
 All other fields specified by AXI4 but not in AXI4-lite and not mentioned in
 this section are not supported by the core when AXI4-lite mode is selected.
 They are not used neither carried across the infrastructure and the user can
@@ -213,7 +226,9 @@ interfaces with two parameters:
 - `MSTx_OSTDREQ_NUM` or `SLVx_OSTDREQ_NUM`: the maximum number of oustanding
   requests the core is capable to store
 - `MSTx_OSTDREQ_SIZE` or `SLVx_OSTDREQ_SIZE`: the number of datpahases of an
-  outstanding requets
+  outstanding requets. Can be useful to save area if a system doesn't need to 
+  use biggest AXI4 payload possible, i.e. if a processor only use [1,2,4,8,16] 
+  dataphases maximum. Default should be `256` beats.
 
 When an inteface enables the CDC support to cross its clock domain, the internal
 buffering is managed with the [DC-FIFO](https://github.com/dpretet/async_fifo)
@@ -281,7 +296,7 @@ help timing closure.
 The figure below illustrates the switching logic dedicated to a slave interface.
 Each slave interface is connected to such switch which sends requests to master
 interface by decoding the address. Completion are routed back from the slave with
-a round robin arbitrer to ensure a fair traffic share. This architecture
+a fair-share round robin arbiter to ensure a fair traffic share. This architecture
 doesn't ensure any ordering rule and the master is responsible to reorder its
 completion if needed by its internal core.
 
@@ -309,7 +324,7 @@ completion if needed by its internal core.
 ### Switching Logic to Master Interfaces
 
 The figure below illustrates the switching logic dedicated to a master interface.
-A round robin arbitration ensures a fair traffic share from the master and the
+A fair-share round robin arbitration ensures a fair traffic share from the master and the
 completion are routed back to the requester by decoding the ID.
 
 ```

test/svut/README.md

@@ -99,11 +99,8 @@ To run the complete testsuite:
 ```bash
 ./run.sh
 ```
-
-The above command disables VCD dump to avoid dropping an insane number of big
-VCD files. Default run always drops them. During the execution, 1000
-AXI4(-lite) requests are injected into each of the 9 scenarios available. A
-default timeout is setup to ensure the whole requests can be completed.
+During the execution, 1000 AXI4(-lite) requests are injected into each of the 9 scenarios available.
+A default timeout is setup to ensure the whole requests can be completed.
 
 The number of requests can be setup to any value, the user just needs to take
 care of the timeout value. The testbench stops after a certain time, even if