Building OoO stage

flow.sh

@@ -54,7 +54,7 @@ help() {
     echo ""
     echo "DESCRIPTION"
     echo ""
-    echo "      This flow handles the different operations available"
+    echo "      This flow handles the different operations available:"
     echo ""
     echo "      ./flow.sh help|-h"
     echo ""
@@ -68,6 +68,10 @@ help() {
     echo ""
     echo "      Launch all available testsuites"
     echo ""
+    echo "      ./flow.sh lint"
+    echo ""
+    echo "      Launch lint analysis with Verilator"
+    echo ""
     echo -e "${NC}"
 }
 
@@ -76,7 +80,7 @@ main() {
     echo ""
     printinfo "Start AXI4-Crossbar Flow"
 
-    # If no argument provided, preint help and exit
+    # If no argument provided, print help and exit
     if [[ $# -eq 0 ]]; then
         help
         exit 1
@@ -103,6 +107,7 @@ main() {
             -I./rtl\
             ./rtl/axicb_mst_if.sv\
             ./rtl/axicb_slv_if.sv\
+            ./rtl/axicb_slv_ooo.sv\
             ./rtl/axicb_slv_switch.sv\
             ./rtl/axicb_slv_switch_rd.sv\
             ./rtl/axicb_slv_switch_wr.sv\
@@ -121,7 +126,9 @@ main() {
     fi
 
     if [[ $1 == "sim" ]]; then
+        # Install SVUT if missing in $PATH
         source script/setup.sh
+        # Run all testsuites against all configurations
         cd "$CURDIR/test/svut"
         ./run.sh --no-debug-log --no-wave
         ret=$?

rtl/axicb_crossbar_top.sv

@@ -77,7 +77,7 @@ module axicb_crossbar_top
         //                    determine which master to route back the
         //                    BRESP/RRESP completions.
         //
-        //   - MSTx_RW: Slect if the interface is
+        //   - MSTx_RW: Select if the interface is
         //         - Read/Write (=0)
         //         - Read-only (=1)
         //         - Write-only (=2)
@@ -708,6 +708,11 @@ module axicb_crossbar_top
                              MST1_ROUTES,
                              MST0_ROUTES};
 
+    localparam MST_OSTDREQ_NUM = {MST3_OSTDREQ_NUM[7:0], 
+                                  MST2_OSTDREQ_NUM[7:0], 
+                                  MST1_OSTDREQ_NUM[7:0], 
+                                  MST0_OSTDREQ_NUM[7:0]};
+
     logic [MST_NB            -1:0] i_awvalid;
     logic [MST_NB            -1:0] i_awready;
     logic [MST_NB*AWCH_W     -1:0] i_awch;
@@ -1147,6 +1152,7 @@ module axicb_crossbar_top
     .MST1_ID_MASK       (MST1_ID_MASK),
     .MST2_ID_MASK       (MST2_ID_MASK),
     .MST3_ID_MASK       (MST3_ID_MASK),
+    .MST_OSTDREQ_NUM    (MST_OSTDREQ_NUM),
     .MST_ROUTES         (MST_ROUTES),
     .MST0_PRIORITY      (MST0_PRIORITY),
     .MST1_PRIORITY      (MST1_PRIORITY),

rtl/axicb_slv_ooo.sv

@@ -0,0 +1,100 @@
+// distributed under the mit license
+// https://opensource.org/licenses/mit-license.php
+
+`timescale 1 ns / 1 ps
+`default_nettype none
+
+module axicb_slv_ooo
+
+    #(
+        // ID width in bits
+        parameter AXI_ID_W = 8,
+        // Number of slave(s)
+        parameter SLV_NB = 4,
+        // Max Outstanding Request
+        parameter MST_OSTDREQ_NUM = 4,
+        // Completion Channels' width (concatenated, either read or write)
+        parameter CCH_W = 8
+    )(
+        // Global interface
+        input  wire                           aclk,
+        input  wire                           aresetn,
+        input  wire                           srst,
+        // Input interface from master:
+        // - address channel handshake (valid/ready)
+        // - full flag (all ID FIFOs full)
+        // - address channel burst length and ID
+        // - slave index targeted (one-hot encoded)
+        // - misrouted flag
+        input  wire                           a_valid,
+        output logic                          a_ready,
+        output logic                          a_full,
+        input  wire  [AXI_ID_W          -1:0] a_id,
+        input  wire  [8                 -1:0] a_len,
+        input  wire  [SLV_NB            -1:0] a_ix,
+        input  wire                           a_mr,
+        // Grant interface:
+        // - enable arbiter
+        // - granted slave
+        // - misrouted flag
+        input  wire                           c_en,
+        output logic [SLV_NB            -1:0] c_grant,
+        output logic                          c_mr,
+        // Completion channel from slaves (either read or write)
+        input  wire  [SLV_NB            -1:0] c_valid,
+        input  wire                           c_ready,
+        input  wire  [CCH_W*SLV_NB      -1:0] c_ch
+    );
+
+    localparam NB_ID = $clog2(AXI_ID_W);
+    localparam FIFO_DEPTH = $clog2(MST_OSTDREQ_NUM);
+    localparam FIFO_WIDTH = 8 + SLV_NB + 1;
+
+    logic [           NB_ID-1:0] push;
+    logic [           NB_ID-1:0] pull;
+    logic [           NB_ID-1:0] full;
+    logic [           NB_ID-1:0] empty;
+    logic [FIFO_WIDTH*NB_ID-1:0] fifo_out;
+
+
+    generate
+
+    for (genvar i=0; i<NB_ID; i++) begin: FIFOS_GEN
+
+        axicb_scfifo 
+        #(
+            .ADDR_WIDTH (FIFO_DEPTH),
+            .DATA_WIDTH (FIFO_WIDTH)
+        )
+        id_fifo 
+        (
+            .aclk     (aclk),
+            .aresetn  (aresetn),
+            .srst     (srst),
+            .flush    (1'b0),
+            .data_in  ({a_len,a_ix,a_mr}),
+            .push     (push[i]),
+            .full     (full[i]),
+            .data_out (fifo_out[i*FIFO_WIDTH+:FIFO_WIDTH]),
+            .pull     (pull[i]),
+            .empty    (empty[i])
+        );
+
+    end
+
+    endgenerate
+
+    // Drive aready by selecting the ID FIFO full
+    // Could be replaced by ORing full vector if AID
+    // doesn't come from a FFD
+    always @ (*) begin
+        a_ready = 1'b0;
+        for (int i=0; i<NB_ID; i++)
+            if (a_id == i[AXI_ID_W-1:0])
+                a_ready = !full[i];
+    end
+
+
+endmodule
+
+`resetall

rtl/axicb_slv_switch.sv

@@ -26,6 +26,9 @@ module axicb_slv_switch
         // Routes allowed to use by this master
         parameter MST_ROUTES = 4'b1_1_1_1,
 
+        // Max Outstanding Request
+        parameter MST_OSTDREQ_NUM = 4,
+
         // Slaves memory mapping
         parameter SLV0_START_ADDR = 0,
         parameter SLV0_END_ADDR = 4095,
@@ -47,7 +50,7 @@ module axicb_slv_switch
         input  wire                           aclk,
         input  wire                           aresetn,
         input  wire                           srst,
-        // Input interfaces from masters
+        // Input interface from master
         input  wire                           i_awvalid,
         output logic                          i_awready,
         input  wire  [AWCH_W            -1:0] i_awch,

rtl/axicb_slv_switch_rd.sv

@@ -26,6 +26,9 @@ module axicb_slv_switch_rd
         // Routes allowed to use by this master
         parameter MST_ROUTES = 4'b1_1_1_1,
 
+        // Max Outstanding Request
+        parameter MST_OSTDREQ_NUM = 4,
+
         // Slaves memory mapping
         parameter SLV0_START_ADDR = 0,
         parameter SLV0_END_ADDR = 4095,
@@ -47,7 +50,7 @@ module axicb_slv_switch_rd
         input  wire                           aclk,
         input  wire                           aresetn,
         input  wire                           srst,
-        // Input interfaces from masters
+        // Input interface from master
         input  wire                           i_arvalid,
         output logic                          i_arready,
         input  wire  [ARCH_W            -1:0] i_arch,
@@ -209,9 +212,9 @@ module axicb_slv_switch_rd
     );
 
 
-    // rch_running prevents mis-routed completion to be routed-back
+    // rch_running prevents misrouted completion to be routed-back
     // the corresponding master.
-    // rlen is the length of the mis-routed packet
+    // rlen is the length of the misrouted packet
     always @ (posedge aclk or negedge aresetn) begin
         if (!aresetn) begin
             rlen <= 8'h0;

rtl/axicb_slv_switch_wr.sv

@@ -26,6 +26,9 @@ module axicb_slv_switch_wr
         // Routes allowed to use by this master
         parameter MST_ROUTES = 4'b1_1_1_1,
 
+        // Max Outstanding Request
+        parameter MST_OSTDREQ_NUM = 4,
+
         // Slaves memory mapping
         parameter SLV0_START_ADDR = 0,
         parameter SLV0_END_ADDR = 4095,
@@ -47,7 +50,7 @@ module axicb_slv_switch_wr
         input  wire                           aclk,
         input  wire                           aresetn,
         input  wire                           srst,
-        // Input interfaces from masters
+        // Input interface from master
         input  wire                           i_awvalid,
         output logic                          i_awready,
         input  wire  [AWCH_W            -1:0] i_awch,

rtl/axicb_switch_top.sv

@@ -45,6 +45,9 @@ module axicb_switch_top
         parameter MST2_PRIORITY = 0,
         parameter MST3_PRIORITY = 0,
 
+        // Masters Outstanding Requests Number
+        parameter [MST_NB*8-1:0] MST_OSTDREQ_NUM = 'h4_4_4_4,
+
         // Slaves memory mapping
         parameter SLV0_START_ADDR = 0,
         parameter SLV0_END_ADDR = 4095,
@@ -261,6 +264,7 @@ module axicb_switch_top
             .AXI_SIGNALING   (AXI_SIGNALING),
             .SLV_NB          (SLV_NB),
             .MST_ROUTES      (MST_ROUTES[i*SLV_NB+:SLV_NB]),
+            .MST_OSTDREQ_NUM (MST_OSTDREQ_NUM[i*8+:8]),
             .TIMEOUT_ENABLE  (TIMEOUT_ENABLE),
             .SLV0_START_ADDR (SLV0_START_ADDR),
             .SLV0_END_ADDR   (SLV0_END_ADDR),

script/setup.sh

@@ -1,6 +1,10 @@
 #!/usr/bin/env bash
 
-# get current script path (applicable even if is a symlink)
+#-------------------------------------------------------------
+# Install SVUT from https://github.com/dpretet/svut if missing
+#-------------------------------------------------------------
+
+# Get current script path (applicable even if is a symlink)
 SOURCE="${BASH_SOURCE[0]}"
 while [ -h "$SOURCE" ]; do
   DIR="$( cd -P "$( dirname "$SOURCE" )" >/dev/null 2>&1 && pwd )"
@@ -9,6 +13,7 @@ while [ -h "$SOURCE" ]; do
 done
 DIR="$( cd -P "$( dirname "$SOURCE" )" >/dev/null 2>&1 && pwd )"
 
+# Clone SVUT and setup $PATH
 if [[ ! $(type svutRun) ]];
 then
     svut_dir="$DIR/.svut"