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Merged VerilogVersion and SystemVerilogVersion.
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@Paebbels
Paebbels committed Aug 1, 2023
1 parent 848c4e4 commit f2923ad
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123 changes: 42 additions & 81 deletions pySVModel/__init__.py
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Original file line number Diff line number Diff line change
Expand Up @@ -34,7 +34,7 @@
:copyright: Copyright 2021-2023 Patrick Lehmann - Bötzingen, Germany
:license: Apache License, Version 2.0
"""
from enum import unique, Enum
from enum import unique, Enum
from typing import Dict, Union

from pyTooling.Decorators import export
Expand All @@ -44,97 +44,50 @@
__email__ = "[email protected]"
__copyright__ = "2021-2023, Patrick Lehmann"
__license__ = "Apache License, Version 2.0"
__version__ = "0.3.6"


@export
@unique
class VerilogVersion(Enum):
Any = -1
Verilog95 = 95
Verilog2001 = 2001
Verilog2005 = 2005

__VERSION_MAPPINGS__: Dict[Union[int, str], Enum] = {
95: Verilog95,
1: Verilog2001,
5: Verilog2005,
1995: Verilog95,
2001: Verilog2001,
2005: Verilog2005,
"Any": Any,
"95": Verilog95,
"01": Verilog2001,
"05": Verilog2005,
"1995": Verilog95,
"2001": Verilog2001,
"2005": Verilog2005,
}

def __init__(self, *_):
"""Patch the embedded MAP dictionary"""
for k, v in self.__class__.__VERSION_MAPPINGS__.items():
if (not isinstance(v, self.__class__)) and (v == self.value):
self.__class__.__VERSION_MAPPINGS__[k] = self

@classmethod
def Parse(cls, value):
try:
return cls.__VERSION_MAPPINGS__[value]
except KeyError:
ValueError("Value '{0!s}' cannot be parsed to member of {1}.".format(value, cls.__name__))

def __lt__(self, other):
return self.value < other.value

def __le__(self, other):
return self.value <= other.value

def __gt__(self, other):
return self.value > other.value

def __ge__(self, other):
return self.value >= other.value

def __ne__(self, other):
return self.value != other.value

def __eq__(self, other):
if (self is self.__class__.Any) or (other is self.__class__.Any):
return True
else:
return self.value == other.value

def __str__(self):
return "Verilog'" + str(self.value)[-2:]

def __repr__(self):
return str(self.value)
__version__ = "0.4.0"


@export
@unique
class SystemVerilogVersion(Enum):
Any = -1

Verilog95 = 95
Verilog2001 = 1
Verilog2005 = 5

SystemVerilog2005 = 2005
SystemVerilog2009 = 2009
SystemVerilog2012 = 2012
SystemVerilog2017 = 2017

__VERSION_MAPPINGS__: Dict[Union[int, str], Enum] = {
5: SystemVerilog2005,
-1: Any,
95: Verilog95,
1: Verilog2001,
5: Verilog2005,
# 5: SystemVerilog2005, # prefer Verilog on numbers below 2000
9: SystemVerilog2009,
12: SystemVerilog2012,
17: SystemVerilog2017,
1995: Verilog95,
2001: Verilog2001,
# 2005: Verilog2005, # prefer SystemVerilog on numbers above 2000
2005: SystemVerilog2005,
2009: SystemVerilog2009,
2012: SystemVerilog2012,
2017: SystemVerilog2017,
"Any": Any,
"05": SystemVerilog2005,
"95": Verilog95,
"01": Verilog2001,
"05": Verilog2005,
# "05": SystemVerilog2005, # prefer Verilog on numbers below 2000
"09": SystemVerilog2009,
"12": SystemVerilog2012,
"17": SystemVerilog2017,
"1995": Verilog95,
"2001": Verilog2001,
# "2005": Verilog2005, # prefer SystemVerilog on numbers above 2000
"2005": SystemVerilog2005,
"2009": SystemVerilog2009,
"2012": SystemVerilog2012,
Expand All @@ -148,35 +101,43 @@ def __init__(self, *_):
self.__class__.__VERSION_MAPPINGS__[k] = self

@classmethod
def Parse(cls, value):
def Parse(cls, value: Union[int, str]) -> "SystemVerilogVersion":
try:
return cls.__VERSION_MAPPINGS__[value]
except KeyError:
ValueError("Value '{0!s}' cannot be parsed to member of {1}.".format(value, cls.__name__))
raise ValueError("Value '{0!s}' cannot be parsed to member of {1}.".format(value, cls.__name__))

def __lt__(self, other):
def __lt__(self, other) -> bool:
return self.value < other.value

def __le__(self, other):
def __le__(self, other) -> bool:
return self.value <= other.value

def __gt__(self, other):
def __gt__(self, other) -> bool:
return self.value > other.value

def __ge__(self, other):
def __ge__(self, other) -> bool:
return self.value >= other.value

def __ne__(self, other):
def __ne__(self, other) -> bool:
return self.value != other.value

def __eq__(self, other):
def __eq__(self, other) -> bool:
if (self is self.__class__.Any) or (other is self.__class__.Any):
return True
else:
return self.value == other.value

def __str__(self):
return "SV'" + str(self.value)[-2:]
def __str__(self) -> str:
if self.value == -1:
return "SV'Any"
elif self.value < self.SystemVerilog2005.value:
return "Verilog'" + str(self.value)[-2:]
else:
return "SV'" + str(self.value)[-2:]

def __repr__(self):
return str(self.value)
def __repr__(self) -> str:
if self.value == -1:
return "Any"

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else:
return str(self.value)

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140 changes: 131 additions & 9 deletions tests/unit/Instantiate.py
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Original file line number Diff line number Diff line change
Expand Up @@ -29,9 +29,9 @@
# ==================================================================================================================== #
#
"""Instantiation tests for the language model."""
from unittest import TestCase
from unittest import TestCase

from pySVModel import VerilogVersion, SystemVerilogVersion
from pySVModel import SystemVerilogVersion


if __name__ == "__main__": # pragma: no cover
Expand All @@ -40,13 +40,135 @@
exit(1)


class Instantiate(TestCase):
def test_VerilogVersion(self):
version = VerilogVersion.Parse("95")
class SVVersion(TestCase):
def test_Any(self):
versions = (
SystemVerilogVersion.Parse(-1),
SystemVerilogVersion.Parse("Any"),
)

self.assertIsNotNone(version)
for version in versions:
self.assertIs(SystemVerilogVersion.Any, version)

def test_SystemVerilogVersion(self):
version = SystemVerilogVersion.Parse("2017")
print()
print(version)
print(version.value)

self.assertIsNotNone(version)
def test_V1995(self):
versions = (
SystemVerilogVersion.Parse(95),
SystemVerilogVersion.Parse(1995),
SystemVerilogVersion.Parse("95"),
SystemVerilogVersion.Parse("1995"),
)

for version in versions:
self.assertIs(SystemVerilogVersion.Verilog95, version)

print()
print(version)
print(version.value)

def test_V2001(self):
versions = (
SystemVerilogVersion.Parse(1),
SystemVerilogVersion.Parse(2001),
SystemVerilogVersion.Parse("01"),
SystemVerilogVersion.Parse("2001"),
)

for version in versions:
self.assertIs(SystemVerilogVersion.Verilog2001, version)

print()
print(version)
print(version.value)

def test_V2005(self):
versions = (
SystemVerilogVersion.Parse(5),
# SystemVerilogVersion.Parse(2005),
SystemVerilogVersion.Parse("05"),
# SystemVerilogVersion.Parse("2005"),
)

for version in versions:
self.assertIs(SystemVerilogVersion.Verilog2005, version)

print()
print(version)
print(version.value)

def test_SV2005(self):
versions = (
# SystemVerilogVersion.Parse(5),
SystemVerilogVersion.Parse(2005),
# SystemVerilogVersion.Parse("05"),
SystemVerilogVersion.Parse("2005"),
)

for version in versions:
self.assertIs(SystemVerilogVersion.SystemVerilog2005, version)

print()
print(version)
print(version.value)

def test_SV2009(self):
versions = (
SystemVerilogVersion.Parse(9),
SystemVerilogVersion.Parse(2009),
SystemVerilogVersion.Parse("09"),
SystemVerilogVersion.Parse("2009"),
)

for version in versions:
self.assertIs(SystemVerilogVersion.SystemVerilog2009, version)

print()
print(version)
print(version.value)

def test_SV2012(self):
versions = (
SystemVerilogVersion.Parse(12),
SystemVerilogVersion.Parse(2012),
SystemVerilogVersion.Parse("12"),
SystemVerilogVersion.Parse("2012"),
)

for version in versions:
self.assertIs(SystemVerilogVersion.SystemVerilog2012, version)

print()
print(version)
print(version.value)

def test_SV2017(self):
versions = (
SystemVerilogVersion.Parse(17),
SystemVerilogVersion.Parse(2017),
SystemVerilogVersion.Parse("17"),
SystemVerilogVersion.Parse("2017"),
)

for version in versions:
self.assertIs(SystemVerilogVersion.SystemVerilog2017, version)

print()
print(version)
print(version.value)

def test_IntError(self):
with self.assertRaises(ValueError):
_ = SystemVerilogVersion.Parse(0)

with self.assertRaises(ValueError):
_ = SystemVerilogVersion.Parse(13)

def test_StrError(self):
with self.assertRaises(ValueError):
_ = SystemVerilogVersion.Parse("0")

with self.assertRaises(ValueError):
_ = SystemVerilogVersion.Parse("13")

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