This project is old. A new version using Verilog with a much cleaner implementation that can run on FPGA is located on: https://github.com/edgardogho/RISC-V2p
This is a RISC-V architecture written in VHDL (sim only). Project runs on Vivado 2019.2.
Most of the RV32I is implemented (except fence, ecall, break and CSR access). All instructions are executed on 4 clock cycle except unaligned data memory access which has penalties. All unaligned access is supported and handled by hardware but breaks the 4 clock cycle per instruction.
Instructions and data are store in a BLOCKRAM. There is a converter program (written in C) that transforms .bin RISC-V files into BLOCKRAM init lines. Shifts are implemented using barrel shifters, ALU is combinational and there are alignment fix units to support unaligned access (data load and store).
This is intended to be used only on simulation (Vivado 2019.2 xsim), not to be implemented in a FPGA. A new version of this design will be implemented in Verilog with FPGA implementation in mind.
This project was designed for UNLaM (www.unlam.edu.ar) as part of the Programmable Logic Research Group (GILP).
