This project implements a simple sales and inventory management system using Verilog hardware description language. The system can calculate the total price, apply discounts, compute the remaining amount, and manage product inventory. It also detects low stock levels and issues alerts. π¨
- π¦ Inventory Management: Manages initial and final stock levels for each product.
- π° Price Calculation: Calculates the total price based on the quantity of products purchased.
- π Discounts: Applies discounts when a specific quantity of products is purchased.
- πΈ Remaining Amount: Computes the remaining amount after payment.
- π¨ Low Stock Alert: Issues alerts when stock levels are low.
The project includes the following modules:
- DFF.v: D Flip-Flop module.
- FMS.v: Finite State Machine module.
- Remaining.v: Remaining amount calculation module.
- Register.v: Register module.
- decoder_3to8.v: 3-to-8 decoder module.
- Comparator.v: Comparator module.
- DiscountCalculator.v: Discount calculation module.
- ProductCounter.v: Product counter module.
- InventoryCounter.v: Inventory counter module.
- LowStockAlert.v: Low stock alert module.
- SalesRegister.v: Sales register module.
To run the project, follow these steps:
- Simulation: Use a Verilog simulator like ModelSim or Icarus Verilog.
- Compile: Compile the Verilog files.
- Run: Execute the testbench to view the simulation results.
iverilog -o output MainModule.v testbench.v
vvp output
The testbench automatically displays the following outputs:
- π Product ID: Product identifier.
- π΅ Price: Unit price of the product.
- π³ Total Price: Total price without discount.
- π Discounted Price: Total price after applying the discount.
- πΈ Amount Paid: Amount paid by the customer.
- π Remaining Amount: Remaining amount after payment.
- π¦ Quantity: Quantity of products purchased.
- π₯ Initial Inventory Counts: Initial stock levels for each product.
- π€ Final Inventory Counts: Final stock levels for each product after purchase.
- π¨ Alerts: Low stock alerts for each product.
- Icarus Verilog: For simulating and running Verilog code.
- GTKWave: For viewing simulation waveforms (optional).
If you'd like to contribute to this project, please follow these steps:
- Fork the project. π΄
- Create a new branch (
git checkout -b feature/YourFeatureName
). πΏ - Commit your changes (
git commit -m 'Add some feature'
). πΎ - Push your changes to your repository (
git push origin feature/YourFeatureName
). π - Open a pull request. π₯