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replace_literals in generate block
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ekiwi committed Jan 9, 2024
1 parent 65ef2fe commit 32eac9e
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Showing 3 changed files with 14 additions and 2 deletions.
4 changes: 4 additions & 0 deletions rtlrepair/repair.py
Original file line number Diff line number Diff line change
Expand Up @@ -109,6 +109,10 @@ def visit_Inout(self, node: vast.Inout):
# by default we ignore any inout declarations
return node

def visit_Instance(self, node: vast.Instance):
# TODO: it would be OK to visit instance connections that are inputs to the instance
return node

def visit_Parameter(self, node: vast.Parameter):
# by default we ignore any parameter declarations
return node
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7 changes: 7 additions & 0 deletions rtlrepair/templates/replace_literals.py
Original file line number Diff line number Diff line change
Expand Up @@ -19,6 +19,13 @@ def __init__(self, vars: dict[str, VarInfo], widths: dict[vast.Node, int]):
super().__init__(name="literal")
self.vars = vars
self.widths = widths
self.in_gen = False

def visit_GenerateStatement(self, node: vast.GenerateStatement):
self.in_gen = True
node = self.generic_visit(node)
self.in_gen = False
return node

def visit_Identifier(self, node: vast.Identifier):
var = self.vars[node.name]
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5 changes: 3 additions & 2 deletions test.py
Original file line number Diff line number Diff line change
Expand Up @@ -169,8 +169,9 @@ def test_d11(self):

def test_d8(self):
""" AXIS Switch with wrong index. Should be fixable by simple literal replacement... """
# TODO: enable some instrumentation in generate blocks
self.synth_cannot_repair(d8_dir, "d8", solver="yices2", init="zero", incremental=True, timeout=60)
changes = self.synth_success(d8_dir, "d8", solver="yices2", init="zero", incremental=True, timeout=60)
# correctly changes constant in one place, but ground truth does change in two places
self.assertEqual(changes, 1)

def test_c4(self):
""" AXIS Async Fifo (we turned the reset into a sync reset) signals ready too early, needs one guard in boolean condition """
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