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expose ScopeOrVarRef and fix some clippy warnings
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ekiwi committed Jan 24, 2025
1 parent 942e046 commit d55e97d
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Showing 5 changed files with 6 additions and 8 deletions.
2 changes: 1 addition & 1 deletion Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@ members = ["wellen", "pywellen"]
default-members = ["wellen"]

[workspace.package]
version = "0.14.0"
version = "0.14.1"
edition = "2021"
# we require the `div_ceil` method on integers
rust-version = "1.73.0"
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2 changes: 1 addition & 1 deletion wellen/src/ghw/hierarchy.rs
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Expand Up @@ -554,7 +554,7 @@ impl VhdlType {

fn from_subtype_unbounded_array(name: StringId, types: &[VhdlType], base: TypeId) -> Self {
// removes the range of the base array
let base_tpe = lookup_concrete_type(&types, base);
let base_tpe = lookup_concrete_type(types, base);
match base_tpe {
VhdlType::Array(_, element_tpe, _) => VhdlType::Array(name, *element_tpe, None),
VhdlType::NineValueVec(_, _) => VhdlType::NineValueVec(name, None),
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4 changes: 2 additions & 2 deletions wellen/src/lib.rs
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Expand Up @@ -57,8 +57,8 @@ pub type Result<T> = std::result::Result<T, WellenError>;

pub use compressed::{CompressedSignal, CompressedTimeTable, Compression};
pub use hierarchy::{
Hierarchy, Scope, ScopeOrVar, ScopeRef, ScopeType, SignalEncoding, SignalRef, Timescale,
TimescaleUnit, Var, VarDirection, VarIndex, VarRef, VarType,
Hierarchy, Scope, ScopeOrVar, ScopeOrVarRef, ScopeRef, ScopeType, SignalEncoding, SignalRef,
Timescale, TimescaleUnit, Var, VarDirection, VarIndex, VarRef, VarType,
};
pub use signals::{Real, Signal, SignalSource, SignalValue, Time, TimeTableIdx};

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4 changes: 1 addition & 3 deletions wellen/src/signals.rs
Original file line number Diff line number Diff line change
Expand Up @@ -212,10 +212,8 @@ impl PartialEq for Signal {
} else {
return false;
}
} else if other_iter.next().is_some() {
return false;
} else {
return true;
return other_iter.next().is_none();
}
}
} else {
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2 changes: 1 addition & 1 deletion wellen/src/wavemem.rs
Original file line number Diff line number Diff line change
Expand Up @@ -901,7 +901,7 @@ pub(crate) fn compress_signal(signal: &Signal) -> Option<(Vec<u8>, SignalEncodin
} else {
// make a copy to allow us to mask out bits
scratch.extend_from_slice(data);
scratch[0] = scratch[0] & mask;
scratch[0] &= mask;
enc.add_n_bit_change(time, &scratch, states);
scratch.clear();
}
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