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fst: add small hack to deal with how NVC encodes bools
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ekiwi committed Jun 12, 2024
1 parent 1e96adb commit f96c38d
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Showing 4 changed files with 40 additions and 2 deletions.
2 changes: 1 addition & 1 deletion Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@ members = ["wellen"]
default-members = ["wellen"]

[workspace.package]
version = "0.9.10"
version = "0.9.11"
edition = "2021"
# we require the `div_ceil` method on integers
rust-version = "1.73.0"
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Binary file added wellen/inputs/nvc/vhdl_test_bool_issue_16.fst
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20 changes: 19 additions & 1 deletion wellen/src/fst.rs
Original file line number Diff line number Diff line change
Expand Up @@ -181,7 +181,25 @@ impl SignalWriter {
}
SignalType::BitVector(len, _) => {
let bits = len.get();
debug_assert_eq!(value.len(), bits as usize);

// nvc will declare boolean signals as 1-bit bit-vectors and then generate
// the strings "true" and "false"
let value = if value.len() > bits as usize && bits == 1 {
match value {
b"true" => b"1",
b"false" => b"0",
_ => value,
}
} else {
value
};

debug_assert_eq!(
value.len(),
bits as usize,
"{}",
String::from_utf8_lossy(value)
);
let local_encoding = check_states(value).unwrap_or_else(|| {
panic!(
"Unexpected signal value: {}",
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20 changes: 20 additions & 0 deletions wellen/tests/fst.rs
Original file line number Diff line number Diff line change
Expand Up @@ -183,3 +183,23 @@ fn test_scope_merging() {
fn test_nvc_xwb_fofb_shaper_filt_tb() {
let _waves = read("inputs/nvc/xwb_fofb_shaper_filt_tb.fst").unwrap();
}

fn load_all_signals(waves: &mut Waveform) {
let all_signals = waves
.hierarchy()
.get_unique_signals_vars()
.iter()
.flatten()
.map(|v| v.signal_ref())
.collect::<Vec<_>>();
waves.load_signals(&all_signals);
}

/// This file was provided by Augusto Fraga Giachero in the following issue:
/// https://github.com/ekiwi/wellen/issues/16
#[test]
fn test_nvc_vhdl_test_bool_issue_16() {
// turns out that NVC needs a little hack to deal with the way it encodes booleans
let mut waves = read("inputs/nvc/vhdl_test_bool_issue_16.fst").unwrap();
load_all_signals(&mut waves);
}

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