This repository contains an HLS design of a moving average IP for PYNQ-based systems.
We relied on Vivado HLS 2019.2 to perform the High-Level Synthesis step, Vivado 2019.2 to generate the bitstream, and Pynq 2.5 to evaluate the IP. In particular, we tested our IP on three Zynq-based platforms, namely Ultra96-V2, Pynq Z2, and ZCU104 .
The HLS folder contains the IP HLS files moving_average.cpp
, moving_average.hpp
, and a testbench testbench.cpp
.
The current version of the IP receives an input stream of integer values and produces an output stream of float averages. The first two elements of the input stream represent the number of input elements and the window of elements to average. Currently, the IP supports moving averages from 1 to 16 elements. You can modify this parameter within the moving_average.hpp
file.
After exporting the IP from Vivado HLS, run Vivado and create an RTL project for your target board. Then, create a block design and add the following IPs:
- Zynq IP (Zynq 7000 or Zynq Ultrascale+ MPSoC according to your board)
- AXI DMA
- Moving Average IP
Once the bitstream is ready, deploy the following files to your target board:
- bitstream file: projectFolder/projectName.runs/impl_1/design_1_wrapper.bit
- Block design file: projectFolder/projectName.srcs/sources_1/bd/design_1/hw_handoff/design_1_bd.tcl
- hwh file: projectFolder/projectName.srcs/sources_1/bd/design_1/hw_handoff/design_1.hwh
Python folder contains two Jupyter notebooks to evaluate the Moving Average IP: moving_average.ipynb
and moving_average_with_class.ipynb
. These files evaluate the IP similar to the HLS testbench using PYNQ APIs. moving_average_with_class.ipynb
wraps the IP usage within a Python class.