rcc: use same name for bus psc

embassy-rs · Sep 16, 2023 · a70aa2f · a70aa2f
1 parent 546aead
commit a70aa2f
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Showing 9 changed files with 218 additions and 20 deletions.
diff --git a/d.ps1 b/d.ps1
@@ -12,7 +12,7 @@ Switch ($CMD)
         rm -r -Force ./sources/ -ErrorAction SilentlyContinue
         git clone https://github.com/embassy-rs/stm32-data-sources.git ./sources/
         cd ./sources/
-        git checkout ca89656b
+        git checkout a2062c088cf299bd3dc5128eeaa96e07fff2087c
         cd ..
     }
     "install-chiptool" {

diff --git a/data/registers/rcc_f1.yaml b/data/registers/rcc_f1.yaml
@@ -462,12 +462,12 @@ fieldset/CFGR:
     description: APB Low speed prescaler (APB1)
     bit_offset: 8
     bit_size: 3
-    enum: PPRE1
+    enum: PPRE
   - name: PPRE2
     description: APB High speed prescaler (APB2)
     bit_offset: 11
     bit_size: 3
-    enum: PPRE1
+    enum: PPRE
   - name: ADCPRE
     description: ADC prescaler
     bit_offset: 14
@@ -783,7 +783,7 @@ enum/PLLXTPRE:
   - name: Div2
     description: HSE clock divided by 2
     value: 1
-enum/PPRE1:
+enum/PPRE:
   bit_size: 3
   variants:
   - name: Div1

diff --git a/data/registers/rcc_f100.yaml b/data/registers/rcc_f100.yaml
@@ -430,12 +430,12 @@ fieldset/CFGR:
     description: APB Low speed prescaler (APB1)
     bit_offset: 8
     bit_size: 3
-    enum: PPRE1
+    enum: PPRE
   - name: PPRE2
     description: APB High speed prescaler (APB2)
     bit_offset: 11
     bit_size: 3
-    enum: PPRE1
+    enum: PPRE
   - name: ADCPRE
     description: ADC prescaler
     bit_offset: 14
@@ -754,7 +754,7 @@ enum/PLLXTPRE:
   - name: Div2
     description: HSE clock divided by 2
     value: 1
-enum/PPRE1:
+enum/PPRE:
   bit_size: 3
   variants:
   - name: Div1

diff --git a/data/registers/rcc_f1cl.yaml b/data/registers/rcc_f1cl.yaml
@@ -409,12 +409,12 @@ fieldset/CFGR:
     description: APB Low speed prescaler (APB1)
     bit_offset: 8
     bit_size: 3
-    enum: PPRE1
+    enum: PPRE
   - name: PPRE2
     description: APB High speed prescaler (APB2)
     bit_offset: 11
     bit_size: 3
-    enum: PPRE1
+    enum: PPRE
   - name: ADCPRE
     description: ADC prescaler
     bit_offset: 14
@@ -832,7 +832,7 @@ enum/PLLXTPRE:
   - name: Div2
     description: HSE clock divided by 2
     value: 1
-enum/PPRE1:
+enum/PPRE:
   bit_size: 3
   variants:
   - name: Div1

diff --git a/data/registers/rcc_h7.yaml b/data/registers/rcc_h7.yaml
@@ -3075,7 +3075,7 @@ fieldset/D1CFGR:
     description: D1 domain APB3 prescaler
     bit_offset: 4
     bit_size: 3
-    enum: DPPRE
+    enum: PPRE
   - name: D1CPRE
     description: D1 domain Core prescaler
     bit_offset: 8
@@ -3169,12 +3169,12 @@ fieldset/D2CFGR:
     description: D2 domain APB1 prescaler
     bit_offset: 4
     bit_size: 3
-    enum: DPPRE
+    enum: PPRE
   - name: D2PPRE2
     description: D2 domain APB2 prescaler
     bit_offset: 8
     bit_size: 3
-    enum: DPPRE
+    enum: PPRE
 fieldset/D3AMR:
   description: RCC D3 Autonomous mode Register
   fields:
@@ -3304,7 +3304,7 @@ fieldset/D3CFGR:
     description: D3 domain APB4 prescaler
     bit_offset: 4
     bit_size: 3
-    enum: DPPRE
+    enum: PPRE
 fieldset/GCR:
   description: Global Control Register
   fields:
@@ -3785,7 +3785,7 @@ enum/DIVP:
   - name: Div128
     description: pll_p_ck = vco_ck / 128
     value: 127
-enum/DPPRE:
+enum/PPRE:
   bit_size: 3
   variants:
   - name: Div1

diff --git a/data/registers/rcc_h7ab.yaml b/data/registers/rcc_h7ab.yaml
@@ -2042,7 +2042,7 @@ fieldset/D1CFGR:
     description: D1 domain APB3 prescaler
     bit_offset: 4
     bit_size: 3
-    enum: DPPRE
+    enum: PPRE
   - name: D1CPRE
     description: D1 domain Core prescaler
     bit_offset: 8
@@ -2141,12 +2141,12 @@ fieldset/D2CFGR:
     description: D2 domain APB1 prescaler
     bit_offset: 4
     bit_size: 3
-    enum: DPPRE
+    enum: PPRE
   - name: D2PPRE2
     description: D2 domain APB2 prescaler
     bit_offset: 8
     bit_size: 3
-    enum: DPPRE
+    enum: PPRE
 fieldset/D3AMR:
   description: RCC D3 Autonomous mode Register
   fields:
@@ -2270,7 +2270,7 @@ fieldset/D3CFGR:
     description: D3 domain APB4 prescaler
     bit_offset: 4
     bit_size: 3
-    enum: DPPRE
+    enum: PPRE
 fieldset/GCR:
   description: Global Control Register
   fields:
@@ -2720,7 +2720,7 @@ enum/DIVP:
   - name: Div128
     description: pll_p_ck = vco_ck / 128
     value: 127
-enum/DPPRE:
+enum/PPRE:
   bit_size: 3
   variants:
   - name: Div1

diff --git a/data/registers/rcc_wb.yaml b/data/registers/rcc_wb.yaml
@@ -1160,14 +1160,17 @@ fieldset/CFGR:
     description: AHB prescaler
     bit_offset: 4
     bit_size: 4
+    enum: HPRE
   - name: PPRE1
     description: PB low-speed prescaler (APB1)
     bit_offset: 8
     bit_size: 3
+    enum: PPRE
   - name: PPRE2
     description: APB high-speed prescaler (APB2)
     bit_offset: 11
     bit_size: 3
+    enum: PPRE
   - name: STOPWUCK
     description: Wakeup from Stop and CSS backup clock selection
     bit_offset: 15
@@ -1651,3 +1654,66 @@ enum/RTCSEL:
   - name: HSE
     description: HSE oscillator clock divided by 32 selected
     value: 3
+enum/PPRE:
+  bit_size: 3
+  variants:
+  - name: Div1
+    description: HCLK not divided
+    value: 0
+  - name: Div2
+    description: HCLK divided by 2
+    value: 4
+  - name: Div4
+    description: HCLK divided by 4
+    value: 5
+  - name: Div8
+    description: HCLK divided by 8
+    value: 6
+  - name: Div16
+    description: HCLK divided by 16
+    value: 7
+enum/HPRE:
+  bit_size: 4
+  variants:
+  - name: Div1
+    description: DCLK not divided
+    value: 0x0
+  - name: Div2
+    description: hclk = SYSCLK divided by 2
+    value: 0x08
+  - name: Div3
+    description: hclk = SYSCLK divided by 3
+    value: 0x01
+  - name: Div4
+    description: hclk = SYSCLK divided by 4
+    value: 0x09
+  - name: Div5
+    description: hclk = SYSCLK divided by 5
+    value: 0x02
+  - name: Div6
+    description: hclk = SYSCLK divided by 6
+    value: 0x05
+  - name: Div8
+    description: hclk = SYSCLK divided by 8
+    value: 0x0a
+  - name: Div10
+    description: hclk = SYSCLK divided by 8
+    value: 0x06
+  - name: Div16
+    description: hclk = SYSCLK divided by 16
+    value: 0x0b
+  - name: Div32
+    description: hclk = SYSCLK divided by 32
+    value: 0x07
+  - name: Div64
+    description: hclk = SYSCLK divided by 64
+    value: 0x0c
+  - name: Div128
+    description: hclk = SYSCLK divided by 128
+    value: 0x0d
+  - name: Div256
+    description: hclk = SYSCLK divided by 256
+    value: 0x0e
+  - name: Div512
+    description: hclk = SYSCLK divided by 256
+    value: 0x0f
diff --git a/data/registers/rcc_wl5.yaml b/data/registers/rcc_wl5.yaml
@@ -1079,14 +1079,17 @@ fieldset/CFGR:
     description: HCLK1 prescaler (CPU1, AHB1, AHB2, and SRAM1.)
     bit_offset: 4
     bit_size: 4
+    enum: HPRE
   - name: PPRE1
     description: PCLK1 low-speed prescaler (APB1)
     bit_offset: 8
     bit_size: 3
+    enum: PPRE
   - name: PPRE2
     description: PCLK2 high-speed prescaler (APB2)
     bit_offset: 11
     bit_size: 3
+    enum: PPRE
   - name: STOPWUCK
     description: Wakeup from Stop and CSS backup clock selection
     bit_offset: 15
@@ -1450,3 +1453,66 @@ enum/RTCSEL:
   - name: HSE
     description: HSE oscillator clock divided by 32 selected
     value: 3
+enum/PPRE:
+  bit_size: 3
+  variants:
+  - name: Div1
+    description: HCLK not divided
+    value: 0
+  - name: Div2
+    description: HCLK divided by 2
+    value: 4
+  - name: Div4
+    description: HCLK divided by 4
+    value: 5
+  - name: Div8
+    description: HCLK divided by 8
+    value: 6
+  - name: Div16
+    description: HCLK divided by 16
+    value: 7
+enum/HPRE:
+  bit_size: 4
+  variants:
+  - name: Div1
+    description: DCLK not divided
+    value: 0x0
+  - name: Div2
+    description: hclk = SYSCLK divided by 2
+    value: 0x08
+  - name: Div3
+    description: hclk = SYSCLK divided by 3
+    value: 0x01
+  - name: Div4
+    description: hclk = SYSCLK divided by 4
+    value: 0x09
+  - name: Div5
+    description: hclk = SYSCLK divided by 5
+    value: 0x02
+  - name: Div6
+    description: hclk = SYSCLK divided by 6
+    value: 0x05
+  - name: Div8
+    description: hclk = SYSCLK divided by 8
+    value: 0x0a
+  - name: Div10
+    description: hclk = SYSCLK divided by 8
+    value: 0x06
+  - name: Div16
+    description: hclk = SYSCLK divided by 16
+    value: 0x0b
+  - name: Div32
+    description: hclk = SYSCLK divided by 32
+    value: 0x07
+  - name: Div64
+    description: hclk = SYSCLK divided by 64
+    value: 0x0c
+  - name: Div128
+    description: hclk = SYSCLK divided by 128
+    value: 0x0d
+  - name: Div256
+    description: hclk = SYSCLK divided by 256
+    value: 0x0e
+  - name: Div512
+    description: hclk = SYSCLK divided by 256
+    value: 0x0f